Searched refs:ADDR_TM_2D_TILED_THIN1 (Results 1 – 6 of 6) sorted by relevance
795 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()801 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()805 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()1063 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()1130 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()1150 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()1156 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()1390 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()1409 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()1461 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
181 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()1132 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()1255 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()1265 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()1389 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()2254 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()2513 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()3026 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()3052 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()3162 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
1392 UINT_32 pipe = ComputePipeFromCoord(x, y, 0, ADDR_TM_2D_TILED_THIN1, 0, FALSE, pTileInfo); in HwlComputeXmaskAddrFromCoord()3316 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOptimizeTileMode()3347 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()3390 pInOut->tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSetPrtTileMode()3427 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()3433 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()3453 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
318 case ADDR_TM_2D_TILED_THIN1: in gfx6_compute_level()431 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) { in gfx6_surface_settings()526 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1; in gfx6_compute_surface()628 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && in gfx6_compute_surface()653 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1); in gfx6_compute_surface()771 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) { in gfx6_compute_surface()
177 ADDR_TM_2D_TILED_THIN1 = 4, ///< A set of macro tiles consist of 8x8 tiles enumerator
2465 ADDR_TM_2D_TILED_THIN1, in HwlComputeXmaskAddrFromCoord()3783 tileMode = ADDR_TM_2D_TILED_THIN1; in DegradeLargeThickTile()