Searched refs:ADDR_TM_PRT_TILED_THIN1 (Results 1 – 5 of 5) sorted by relevance
797 tileMode == ADDR_TM_PRT_TILED_THIN1 || in HwlComputeFmaskInfo()946 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOptimizeTileMode()972 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOptimizeTileMode()1020 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOverrideTileMode()1072 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOverrideTileMode()1183 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlSelectTileMode()1229 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlSetPrtTileMode()1374 case ADDR_TM_PRT_TILED_THIN1: in HwlSetupTileInfo()1393 case ADDR_TM_PRT_TILED_THIN1: in HwlSetupTileInfo()1415 case ADDR_TM_PRT_TILED_THIN1: in HwlSetupTileInfo()[all …]
187 case ADDR_TM_PRT_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()1134 case ADDR_TM_PRT_TILED_THIN1: in ComputeSurfaceMipLevelTileMode()1395 case ADDR_TM_PRT_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()2260 case ADDR_TM_PRT_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
3346 case ADDR_TM_PRT_TILED_THIN1: in HwlOverrideTileMode()
192 ADDR_TM_PRT_TILED_THIN1 = 19, ///< No bank/pipe rotation or hashing beyond macrotile size enumerator
3798 tileMode = ADDR_TM_PRT_TILED_THIN1; in DegradeLargeThickTile()