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Searched refs:ADDS (Results 1 – 25 of 59) sorted by relevance

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/external/vixl/test/aarch32/config/
Dcond-rdlow-rnlow-operand-immediate-t32.json37 "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1
38 // ADDS{<q>} <Rdn>, #<imm8> ; T2
39 // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
136 "Adds", // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
174 "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1
Dcond-rd-rn-operand-const-a32.json34 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
35 // ADDS{<c>}{<q>} {<Rd>}, SP, #<const> ; A1
Dcond-rd-rn-operand-const-t32.json40 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T3
41 // ADDS{<c>}{<q>} {<Rd>}, SP, #<const> ; T3
Dcond-rd-rn-operand-rm-shift-amount-1to32-a32.json33 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
34 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
Dcond-rd-rn-operand-rm-shift-amount-1to31-a32.json33 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
34 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
Dcond-rd-rn-operand-rm-shift-amount-1to31-t32.json37 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
38 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
Dcond-rd-rn-operand-rm-shift-amount-1to32-t32.json37 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
38 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
Dcond-rd-rn-operand-rm-t32.json59 "Adds", // ADDS{<q>} {<Rd>}, <Rn>, <Rm> ; T1
60 // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
61 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
Dcond-rd-rn-operand-rm-a32.json42 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
43 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
Dcond-rd-rn-operand-rm-shift-rs-a32.json32 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
/external/libopus/celt/arm/
Dcelt_pitch_xcorr_arm_gnu.s125 ADDS r12, r12, #2
144 ADDS r12, r12, #1
313 ADDS r2, r2, #4
397 ADDS r12, r12, #4
444 ADDS r1, r1, #2
470 ADDS r12, r12, #2
483 ADDS r12, r12, #1
509 ADDS r1, r1, #1
531 ADDS r12, r12, #2
538 ADDS r12, r12, #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dnegative-immediates.s57 ADDS r0, r1, #0xFFFFFF00
60 # CHECK-DISABLED: ADDS
61 ADDS.W r0, r1, #0xFFFFFF00
64 # CHECK-DISABLED: ADDS.W
Dthumb2-narrow-dp.ll15 ADDS r0, r0, #5 // T1
17 ADDS r1, r1, #8 // T2
19 ADDS.W r1, r1, #8 // .w => T3
21 ADDS r8, r8, #8 // T3
43 ADDS r0, r2, r1 // ADDS has T1 narrow 3 operand
45 ADDS r2, r2, r1 // ADDS has T1 narrow 3 operand
/external/tremolo/Tremolo/
DbitwiseARM.s68 ADDS r10,r2,r1 @ r10= bitsLeftInSegment + bits (i.e.
151 ADDS r14,r14,r10 @ r14= length in bits-bits to skip
196 ADDS r10,r10,r2 @ r10= bits left in word after skip
200 ADDS r2,r2,r12,LSL #3 @ r2 = length in bits after advance
260 ADDS r10,r2,r1 @ r10= bitsLeftInSegment + bits (i.e.
391 ADDS r14,r14,r10 @ r14= length in bits-bits to skip
Ddpen.s102 ADDS r1, r1, #1 @ r1 = i-read++ (i-read<0 => i<read)
127 ADDS r1, r1, #1 @ r1 = i++
159 ADDS r1, r1, #1 @ r1 = i-read++ (i-read<0 => i<read)
185 ADDS r1, r1, #1 @ r1 = i++
217 ADDS r1, r1, #1 @ r1 = i-read++ (i-read<0 => i<read)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/
Doptionaldef-scheduling.ll14 ; a flag-setting instruction in between an ADDS and the corresponding ADC.
Dlong.ll136 define i64 @f9d(i64 %x, i32 %y) { ; SUBS with small negative imm => ADDS imm
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h328 X86_INTRINSIC_DATA(avx2_padds_b, INTR_TYPE_2OP, X86ISD::ADDS, 0),
329 X86_INTRINSIC_DATA(avx2_padds_w, INTR_TYPE_2OP, X86ISD::ADDS, 0),
680 X86_INTRINSIC_DATA(avx512_mask_padds_b_128, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
681 X86_INTRINSIC_DATA(avx512_mask_padds_b_256, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
682 X86_INTRINSIC_DATA(avx512_mask_padds_b_512, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
683 X86_INTRINSIC_DATA(avx512_mask_padds_w_128, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
684 X86_INTRINSIC_DATA(avx512_mask_padds_w_256, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
685 X86_INTRINSIC_DATA(avx512_mask_padds_w_512, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
1187 X86_INTRINSIC_DATA(sse2_padds_b, INTR_TYPE_2OP, X86ISD::ADDS, 0),
1188 X86_INTRINSIC_DATA(sse2_padds_w, INTR_TYPE_2OP, X86ISD::ADDS, 0),
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h281 X86_INTRINSIC_DATA(avx2_padds_b, INTR_TYPE_2OP, X86ISD::ADDS, 0),
282 X86_INTRINSIC_DATA(avx2_padds_w, INTR_TYPE_2OP, X86ISD::ADDS, 0),
866 X86_INTRINSIC_DATA(avx512_mask_padds_b_128, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
867 X86_INTRINSIC_DATA(avx512_mask_padds_b_256, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
868 X86_INTRINSIC_DATA(avx512_mask_padds_b_512, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
869 X86_INTRINSIC_DATA(avx512_mask_padds_w_128, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
870 X86_INTRINSIC_DATA(avx512_mask_padds_w_256, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
871 X86_INTRINSIC_DATA(avx512_mask_padds_w_512, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
1892 X86_INTRINSIC_DATA(sse2_padds_b, INTR_TYPE_2OP, X86ISD::ADDS, 0),
1893 X86_INTRINSIC_DATA(sse2_padds_w, INTR_TYPE_2OP, X86ISD::ADDS, 0),
/external/llvm/test/MC/ARM/
Dthumb2-narrow-dp.ll15 ADDS r0, r0, #5 // T1
17 ADDS r1, r1, #8 // T2
19 ADDS.W r1, r1, #8 // .w => T3
21 ADDS r8, r8, #8 // T3
43 ADDS r0, r2, r1 // ADDS has T1 narrow 3 operand
45 ADDS r2, r2, r1 // ADDS has T1 narrow 3 operand
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dcond-br-tuning.ll6 ; CMN is an alias of ADDS.
/external/v8/src/arm64/
Dconstants-arm64.h513 ADDS = ADD | AddSubSetFlagsBit, enumerator
520 V(ADDS), \
565 ADCS_w = AddSubWithCarryFixed | ADDS,
566 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-aliases.s58 ; ADDS to WZR/XZR is a CMN
/external/llvm/test/MC/AArch64/
Darm64-aliases.s58 ; ADDS to WZR/XZR is a CMN
/external/vixl/src/aarch64/
Dconstants-aarch64.h478 ADDS = ADD | AddSubSetFlagsBit, enumerator
485 V(ADDS), \
530 ADCS_w = AddSubWithCarryFixed | ADDS,
531 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,

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