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Searched refs:ADDSUB (Results 1 – 12 of 12) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h297 X86_INTRINSIC_DATA(avx_addsub_pd_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
298 X86_INTRINSIC_DATA(avx_addsub_ps_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
1222 X86_INTRINSIC_DATA(sse3_addsub_pd, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
1223 X86_INTRINSIC_DATA(sse3_addsub_ps, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
DX86ISelLowering.h210 ADDSUB, enumerator
DX86InstrFragmentsSIMD.td449 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
DX86ISelLowering.cpp7794 return DAG.getNode(X86ISD::ADDSUB, DL, VT, Opnd0, Opnd1); in lowerToAddSubOrFMAddSub()
26141 case X86ISD::ADDSUB: return "X86ISD::ADDSUB"; in getTargetNodeName()
31084 return DAG.getNode(X86ISD::ADDSUB, DL, VT, Opnd0, Opnd1); in combineShuffleToAddSubOrFMAddSub()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dsse3-avx-addsub.ll6 ; Test ADDSUB ISel patterns.
Dfmaddsub-combine.ll6 ; This test checks the fusing of MUL + ADDSUB to FMADDSUB.
/external/llvm/test/CodeGen/X86/
Dsse3-avx-addsub.ll6 ; Test ADDSUB ISel patterns.
/external/llvm/lib/Target/X86/
DX86ISelLowering.h199 ADDSUB, enumerator
DX86SchedHaswell.td2015 "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)r(Y)?",
2032 "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)m(Y)?",
DX86InstrFragmentsSIMD.td454 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
DX86ISelLowering.cpp6362 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1); in LowerToAddSub()
22307 case X86ISD::ADDSUB: return "X86ISD::ADDSUB"; in getTargetNodeName()
26036 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS); in combineShuffleToAddSub()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc8298 // FastEmit functions for X86ISD::ADDSUB.
11986 case X86ISD::ADDSUB: return fastEmit_X86ISD_ADDSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);