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Searched refs:ADDVI_W (Results 1 – 11 of 11) sorted by relevance

/external/webp/src/dsp/
Dmsa_macro.h27 #define ADDVI_W(a, b) __msa_addvi_w((v4i32)a, b) macro
38 #define ADDVI_W(a, b) (a + b) macro
1146 out0 = (RTYPE)ADDVI_W(in0, in1); \
1147 out1 = (RTYPE)ADDVI_W(in2, in3); \
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc71 570449319U, // ADDVI_W
1785 0U, // ADDVI_W
4818 // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,...
DMipsGenDisassemblerTables.inc1365 /* 3965 */ MCD_OPC_Decode, 54, 101, // Opcode: ADDVI_W
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenAsmWriter.inc1800 268460310U, // ADDVI_W
4431 4U, // ADDVI_W
6962 // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG...
DMipsGenMCCodeEmitter.inc585 UINT64_C(2017460230), // ADDVI_W
3710 case Mips::ADDVI_W:
8311 Feature_HasStdEnc | Feature_HasMSA | 0, // ADDVI_W = 572
DMipsGenDAGISel.inc16380 /* 30049*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_W), 0,
16383 … // Dst: (ADDVI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
16386 /* 30061*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_W), 0,
16389 … // Dst: (ADDVI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
DMipsGenInstrInfo.inc587 ADDVI_W = 572,
4632 …, 3, 1, 4, 520, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #572 = ADDVI_W
DMipsGenDisassemblerTables.inc3829 /* 5328 */ MCD::OPC_Decode, 188, 4, 237, 1, // Opcode: ADDVI_W
DMipsGenAsmMatcher.inc5165 …{ 445 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,…
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td2739 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td2746 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;