Searched refs:AHB1_ABP1_DIV_DEFAULT (Results 1 – 4 of 4) sorted by relevance
42 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); in clock_init_safe()
48 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); in clock_init_safe()
265 #define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ macro267 #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ macro
183 #define AHB1_ABP1_DIV_DEFAULT 0x00002190 macro