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Searched refs:AIPS0_BASE_ADDR (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-vf610/
Dimx-regs.h14 #define AIPS0_BASE_ADDR 0x40000000 macro
18 #define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
19 #define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
20 #define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
21 #define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
22 #define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
23 #define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
24 #define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
25 #define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
26 #define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
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/external/u-boot/arch/arm/include/asm/arch-s32v234/
Dimx-regs.h14 #define AIPS0_BASE_ADDR (0x40000000UL) macro
18 #define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000)
19 #define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
20 #define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
21 #define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000)
22 #define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
23 #define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
24 #define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
25 #define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
26 #define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000)
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