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Searched refs:AIPS1_BASE_ADDR (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-s32v234/
Dimx-regs.h15 #define AIPS1_BASE_ADDR (0x40080000UL) macro
66 #define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000)
67 #define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000)
68 #define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000)
69 #define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000)
70 #define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000)
71 #define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000)
72 #define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000)
73 #define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000)
74 #define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000)
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/external/u-boot/arch/arm/include/asm/arch-mx5/
Dimx-regs.h16 #define AIPS1_BASE_ADDR 0x73F00000 macro
26 #define AIPS1_BASE_ADDR 0x53F00000 macro
59 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
60 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
61 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
62 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
63 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
64 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
65 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
66 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
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/external/u-boot/arch/arm/include/asm/arch-vf610/
Dimx-regs.h15 #define AIPS1_BASE_ADDR 0x40080000 macro
94 #define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)
95 #define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
96 #define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
97 #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
98 #define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
99 #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
100 #define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
101 #define DCU1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00058000)
102 #define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000)
/external/u-boot/arch/arm/include/asm/arch-mx35/
Dimx-regs.h24 #define AIPS1_BASE_ADDR 0x43F00000 macro
25 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
Dlowlevel_macro.S23 ldr r0, =AIPS1_BASE_ADDR
/external/u-boot/arch/arm/mach-imx/
Dinit.c17 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; in init_aips()
/external/u-boot/arch/arm/include/asm/arch-mx8m/
Dimx-regs.h21 #define AIPS1_BASE_ADDR 0x301F0000 macro
/external/u-boot/arch/arm/mach-imx/mx5/
Dlowlevel_init.S62 ldr r0, =AIPS1_BASE_ADDR
/external/u-boot/arch/arm/include/asm/arch-mx6/
Dimx-regs.h134 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR macro
/external/u-boot/arch/arm/include/asm/arch-mx7/
Dimx-regs.h201 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR macro