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Searched refs:AIPS1_OFF_BASE_ADDR (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-mx6/
Dimx-regs.h172 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) macro
173 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
174 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
175 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
176 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
177 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
178 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
180 #define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
181 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
182 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
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/external/u-boot/arch/arm/include/asm/arch-mx7/
Dimx-regs.h86 #define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000) macro
88 #define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR
89 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000)
90 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000)
91 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000)
92 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000)
93 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000)
94 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000)
95 #define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000)
96 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000)
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