| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_conv_ergtoamplitude.s | 48 ANDS R11, R11, R14
75 ANDS R11, R11, R14
103 ANDS R11, R11, R14
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| D | ixheaacd_autocorr_st2.s | 114 ANDS r0, r3, #0x01
358 ANDS r5 , r3 , #3
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| D | ixheaacd_conv_ergtoamplitudelp.s | 102 ANDS R6, R6, R10
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| D | ixheaacd_tns_ar_filter_fixed_32x16.s | 34 ANDS r5, r4, #3
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-ands-bad-peephole.ll | 2 ; Check that ANDS (tst) is not merged with ADD when the immediate
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-ands-bad-peephole.ll | 2 ; Check that ANDS (tst) is not merged with ADD when the immediate
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 106 ANDS r0, r2, r1 // Must be wide - 3 distinct registers
107 ANDS r2, r2, r1 // Should choose narrow
108 ANDS r2, r1, r2 // Should choose narrow - commutative
109 ANDS.W r0, r0, r1 // Explicitly wide
110 ANDS.W r3, r1, r3
112 ANDS r7, r7, r1 // Should use narrow
113 ANDS r7, r1, r7 // Commutative
114 ANDS r8, r1, r8 // high registers so must use wide encoding
115 ANDS r8, r8, r1
116 ANDS r0, r8, r0
[all …]
|
| D | negative-immediates.s | 109 ANDS r0, r1, #0xFFFFFF00
112 # CHECK-DISABLED: ANDS
|
| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 106 ANDS r0, r2, r1 // Must be wide - 3 distinct registers
107 ANDS r2, r2, r1 // Should choose narrow
108 ANDS r2, r1, r2 // Should choose narrow - commutative
109 ANDS.W r0, r0, r1 // Explicitly wide
110 ANDS.W r3, r1, r3
112 ANDS r7, r7, r1 // Should use narrow
113 ANDS r7, r1, r7 // Commutative
114 ANDS r8, r1, r8 // high registers so must use wide encoding
115 ANDS r8, r8, r1
116 ANDS r0, r8, r0
[all …]
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-rm-t32.json | 66 "Ands", // ANDS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
67 // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-const-a32.json | 37 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
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| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 34 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
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| D | cond-rd-rn-operand-const-t32.json | 43 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 40 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 40 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-a32.json | 45 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 585 ANDS = 0x60000000, enumerator
586 BICS = ANDS | NOT
600 ANDS_w_imm = LogicalImmediateFixed | ANDS,
601 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
627 ANDS_w = LogicalShiftedFixed | ANDS,
628 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
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| D | instructions-arm64.h | 278 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) { in RdMode()
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | arm-and-tst-peephole.ll | 68 ; generates a predicated ANDS instruction. Check that the predicate is printed
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 550 ANDS = 0x60000000, enumerator
551 BICS = ANDS | NOT
565 ANDS_w_imm = LogicalImmediateFixed | ANDS,
566 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
592 ANDS_w = LogicalShiftedFixed | ANDS,
593 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
|
| /external/llvm/test/CodeGen/ARM/ |
| D | arm-and-tst-peephole.ll | 81 ; generates a predicated ANDS instruction. Check that the predicate is printed
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 309 def : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "AD(C|D)S?ri", "ANDS?ri",
315 "ANDS?rr", "BICS?rr", "CRC", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr",
319 "ANDS?rsi", "BICS?rsi", "EORrsi", "ORRrsi", "RSBrsi", "RSCrsi", "SBCrsi",
323 (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr",
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | arm-and-tst-peephole.ll | 80 ; generates a predicated ANDS instruction. Check that the predicate is printed
|