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Searched refs:APSR_nzcvq (Results 1 – 25 of 69) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dmsr-it-block.ll23 ; V7A: msr APSR_nzcvq, {{r[0-9]+}}
24 ; V7A: msr APSR_nzcvq, {{r[0-9]+}}
44 ; V7A: msr APSR_nzcvq, {{r[0-9]+}}
45 ; V7A: msr APSR_nzcvq, {{r[0-9]+}}
Dspecial-reg-acore.ll30 ; ACORE: msr APSR_nzcvq, r0
36 ; ACORE: msr APSR_nzcvq, r0
Dspecial-reg.ll55 ; ACORE: msr APSR_nzcvq, r0
Dcopy-cpsr.ll24 ; CHECK-ARM: msr APSR_nzcvq, [[TMP]] @ encoding: [0x0{{[0-9a-f]}},0xf0,0x28,0xe1]
/external/llvm/test/CodeGen/ARM/
Dspecial-reg-acore.ll30 ; ACORE: msr APSR_nzcvq, r0
36 ; ACORE: msr APSR_nzcvq, r0
Dspecial-reg.ll55 ; ACORE: msr APSR_nzcvq, r0
Dcopy-cpsr.ll24 ; CHECK-ARM: msr APSR_nzcvq, [[TMP]] @ encoding: [0x0{{[0-9a-f]}},0xf0,0x28,0xe1]
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs388 0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5
390 0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5
391 0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5
402 0x00,0xf0,0x28,0xe1 = msr APSR_nzcvq, r0
404 0x00,0xf0,0x28,0xe1 = msr APSR_nzcvq, r0
405 0x00,0xf0,0x28,0xe1 = msr APSR_nzcvq, r0
/external/vixl/test/aarch32/
Dtest-simulator-cond-rd-rn-rm-sel-t32.cc454 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
466 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-sel-a32.cc454 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
466 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-q-t32.cc461 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
473 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-q-a32.cc461 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
473 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-ge-t32.cc477 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
489 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-ge-a32.cc477 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
489 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
Dtest-simulator-cond-rd-operand-const-a32.cc523 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
Dtest-simulator-cond-rd-operand-imm16-t32.cc476 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
Dtest-simulator-cond-rd-operand-const-t32.cc638 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-ror-amount-a32.cc625 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-t32.cc560 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-a32.cc560 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
/external/vixl/src/aarch32/
Dinstructions-aarch32.cc222 case APSR_nzcvq: in GetName()
Dinstructions-aarch32.h840 APSR_nzcvq = 0x08, enumerator
850 CPSR_f = APSR_nzcvq,
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1428 msr APSR_nzcvq, #5
1440 msr APSR_nzcvq, #42, #2
1447 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1448 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1449 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1451 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1452 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1464 @ CHECK: msr APSR_nzcvq, #2147483658 @ encoding: [0x2a,0xf1,0x28,0xe3]
1474 msr APSR_nzcvq, r0
1486 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1430 msr APSR_nzcvq, #5
1442 msr APSR_nzcvq, #42, #2
1449 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1450 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1451 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1453 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1454 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1466 @ CHECK: msr APSR_nzcvq, #2147483658 @ encoding: [0x2a,0xf1,0x28,0xe3]
1476 msr APSR_nzcvq, r0
1488 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s914 msr APSR_nzcvq, #5
926 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
928 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
929 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
944 msr APSR_nzcvq, r0
956 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
958 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
959 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]

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