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Searched refs:AR933X_PLL_CLK_CTRL_REG (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/mips/mach-ath79/ar933x/
Dlowlevel_init.S159 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
273 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
Dclk.c56 val = readl(regs + AR933X_PLL_CLK_CTRL_REG); in get_clocks()
/external/u-boot/arch/mips/mach-ath79/include/mach/
Dar71xx_regs.h331 #define AR933X_PLL_CLK_CTRL_REG 0x08 macro