Searched refs:ASRV (Results 1 – 13 of 13) sorted by relevance
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 75 #define ASRV 0x9ac02800 macro
788 FAIL_IF(push_inst(compiler, (ASRV ^ inv_bits) | RD(dst) | RN(arg1) | RM(arg2))); in emit_op_imm()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 169 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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| D | AArch64InstrInfo.td | 702 defm ASRV : Shift<0b10, "asr", sra>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 171 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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| D | AArch64SchedFalkorDetails.td | 1232 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(LSLV|LSRV|ASRV|RORV)(W|X)r$")>;
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| D | AArch64InstrInfo.td | 901 defm ASRV : Shift<0b10, "asr", sra>;
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1059 ASRV = ASRV_w, enumerator
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| D | disasm-arm64.cc | 605 FORMAT(ASRV, "asr"); in VisitDataProcessing2Source()
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| D | assembler-arm64.cc | 1289 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1231 ASRV = ASRV_w, enumerator
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| D | disasm-aarch64.cc | 776 FORMAT(ASRV, "asr"); in VisitDataProcessing2Source()
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| D | assembler-aarch64.cc | 646 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 89 ### ASRV ### subsection
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