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Searched refs:A_1 (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/lib/
Duldivmod.S18 A_1 .req r1 label
48 @ Test if A_1 == B_1 == 0
49 orrs ip, A_1, B_1
58 teq A_1, #0
59 clz D_0, A_1
98 cmpcc B_1, A_1
112 cmpcc B_1, A_1
127 cmp A_1, B_1
132 sbc A_1, A_1, B_1
138 orrs ip, A_1, A_0
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/CodeGenPrepare/NVPTX/
Dbypass-slow-div-special-cases.ll10 ; CHECK-NEXT: [[A_1:%.*]] = zext i32 [[A:%.*]] to i64
11 ; CHECK-NEXT: [[A_2:%.*]] = sub i64 -1, [[A_1]]
53 ; CHECK-NEXT: [[A_1:%.*]] = and i64 [[A:%.*]], 4294967295
55 ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A_1]] to i32
73 ; CHECK-NEXT: [[A_1:%.*]] = zext i32 [[A:%.*]] to i64
74 ; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[A_1]], [[B:%.*]]
77 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[A_1]] to i32
84 ; CHECK-NEXT: [[TMP11:%.*]] = phi i64 [ [[TMP8]], [[TMP2]] ], [ [[A_1]], [[TMP0]] ]
/external/clang/test/Analysis/
DPR24184.cpp61 struct A_1 { struct
71 A_1 HashAlgId; argument
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/AArch64/
Dtranspose.ll39 ; CHECK-NEXT: [[A_1:%.*]] = getelementptr i64, i64* %a, i64 1
43 ; CHECK-NEXT: [[V0_1:%.*]] = load i64, i64* [[A_1]], align 8