Home
last modified time | relevance | path

Searched refs:AddRegFrm (Results 1 – 25 of 29) sorted by relevance

12

/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrFPStack.td218 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
220 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
222 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
332 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
334 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
336 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
338 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
340 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
342 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
344 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
[all …]
DX86InstrInfo.td672 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
674 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
688 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
690 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
714 def POP64r : I<0x58, AddRegFrm,
720 def PUSH64r : I<0x50, AddRegFrm,
757 def BSWAP32r : I<0xC8, AddRegFrm,
762 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
855 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
858 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
[all …]
DX86InstrArithmetic.td388 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
392 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
467 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
471 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
DX86CodeEmitter.cpp819 case X86II::AddRegFrm: { in emitInstruction()
DX86RegisterInfo.td393 // GR32_NOAX - GR32 registers except EAX. Used by AddRegFrm of XCHG32 in 64-bit
DX86InstrFormats.td22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h187 AddRegFrm = 2, enumerator
471 case X86II::AddRegFrm: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp912 case X86II::AddRegFrm: in EncodeInstruction()
/external/llvm/test/TableGen/
DTargetInstrInfo.td49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
93 "mov $dst, $src", 0xB0, AddRegFrm,
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DTargetInstrInfo.td49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
93 "mov $dst, $src", 0xB0, AddRegFrm,
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
93 "mov $dst, $src", 0xB0, AddRegFrm,
/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp46 AddRegFrm = 2, enumerator
630 case X86Local::AddRegFrm: in emitInstructionSpecifier()
888 if (Form == X86Local::AddRegFrm) { in emitDecodePath()
955 if (Form == X86Local::AddRegFrm) { in emitDecodePath()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h235 AddRegFrm = 2, enumerator
668 case X86II::AddRegFrm: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp987 case X86II::AddRegFrm: in DetermineREXPrefix()
1271 case X86II::AddRegFrm: in encodeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h253 AddRegFrm = 2, enumerator
702 case X86II::AddRegFrm: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1059 case X86II::AddRegFrm: in DetermineREXPrefix()
1359 case X86II::AddRegFrm: in encodeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DX86RecognizableInstr.h98 AddRegFrm = 2, enumerator
DX86RecognizableInstr.cpp491 case X86Local::AddRegFrm: in emitInstructionSpecifier()
720 case X86Local::AddRegFrm: in emitDecodePath()
772 if (Form == X86Local::AddRegFrm) { in emitDecodePath()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp96 AddRegFrm = 2, enumerator
596 case X86Local::AddRegFrm: in emitInstructionSpecifier()
884 if (Form == X86Local::AddRegFrm) { in emitDecodePath()
/external/llvm/lib/Target/X86/
DX86InstrInfo.td1094 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1096 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1109 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1111 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1184 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1192 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1237 def BSWAP32r : I<0xC8, AddRegFrm,
1242 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1370 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1373 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
[all …]
DX86InstrArithmetic.td475 def INC16r_alt : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
478 def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
521 def DEC16r_alt : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
524 def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
DX86RegisterInfo.td398 // GR32_NOAX - GR32 registers except EAX. Used by AddRegFrm of XCHG32 in 64-bit
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrInfo.td1201 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
1203 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>,
1221 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
1223 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>,
1297 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>,
1309 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>,
1359 def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1362 def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1367 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1495 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
[all …]
DX86InstrArithmetic.td445 def INC16r_alt : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
448 def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
491 def DEC16r_alt : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
494 def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DWritingAnLLVMBackend.rst1843 case X86II::AddRegFrm: // for instructions that have one register operand
1878 for the ``X86II::AddRegFrm`` case, the first data emitted (by ``emitByte``) is
1889 case X86II::AddRegFrm:

12