Home
last modified time | relevance | path

Searched refs:AreConsecutive (Results 1 – 6 of 6) sorted by relevance

/external/vixl/test/aarch64/
Dtest-api-aarch64.cc213 VIXL_CHECK(AreConsecutive(b0, NoVReg)); in TEST()
214 VIXL_CHECK(AreConsecutive(b1, b2)); in TEST()
215 VIXL_CHECK(AreConsecutive(b3, b4, b5)); in TEST()
216 VIXL_CHECK(AreConsecutive(b6, b7, b8, b9)); in TEST()
217 VIXL_CHECK(AreConsecutive(h10, NoVReg)); in TEST()
218 VIXL_CHECK(AreConsecutive(h11, h12)); in TEST()
219 VIXL_CHECK(AreConsecutive(h13, h14, h15)); in TEST()
220 VIXL_CHECK(AreConsecutive(h16, h17, h18, h19)); in TEST()
221 VIXL_CHECK(AreConsecutive(s20, NoVReg)); in TEST()
222 VIXL_CHECK(AreConsecutive(s21, s22)); in TEST()
[all …]
/external/v8/src/arm64/
Dassembler-arm64.cc279 bool AreConsecutive(const VRegister& reg1, const VRegister& reg2, in AreConsecutive() function
2543 DCHECK(AreConsecutive(vn, vn2)); in tbl()
2553 DCHECK(AreConsecutive(vn, vn2, vn3)); in tbl()
2564 DCHECK(AreConsecutive(vn, vn2, vn3, vn4)); in tbl()
2577 DCHECK(AreConsecutive(vn, vn2)); in tbx()
2587 DCHECK(AreConsecutive(vn, vn2, vn3)); in tbx()
2598 DCHECK(AreConsecutive(vn, vn2, vn3, vn4)); in tbx()
2737 DCHECK(AreConsecutive(vt, vt2)); in ld1()
2746 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld1()
2757 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld1()
[all …]
Dassembler-arm64.h502 bool AreConsecutive(const VRegister& reg1, const VRegister& reg2,
/external/vixl/src/aarch64/
Dassembler-aarch64.cc341 VIXL_ASSERT(AreConsecutive(vn, vn2)); in tbl()
354 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3)); in tbl()
368 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3, vn4)); in tbl()
388 VIXL_ASSERT(AreConsecutive(vn, vn2)); in tbx()
401 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3)); in tbx()
415 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3, vn4)); in tbx()
1633 VIXL_ASSERT(AreConsecutive(rs, rs1)); \ in COMPARE_AND_SWAP_W_LIST()
1634 VIXL_ASSERT(AreConsecutive(rt, rt1)); \ in COMPARE_AND_SWAP_W_LIST()
1908 VIXL_ASSERT(AreConsecutive(vt, vt2)); in ld1()
1920 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3)); in ld1()
[all …]
Doperands-aarch64.h524 bool AreConsecutive(const CPURegister& reg1,
543 bool AreConsecutive(const VRegister& reg1,
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc2107 DCHECK(AreConsecutive(src0, src1)); in AssembleArchInstruction()