Searched refs:ArgRegIdx (Results 1 – 1 of 1) sorted by relevance
1121 unsigned ArgRegIdx = 0; in LowerFormalArguments() local1180 ++ArgRegIdx; in LowerFormalArguments()1221 for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) { in LowerFormalArguments()1225 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass); in LowerFormalArguments()1293 unsigned ArgRegIdx = 0; in LowerCall() local1300 for (; ArgRegIdx != NumOps; ++ArgRegIdx) { in LowerCall()1301 SDValue Arg = OutVals[ArgRegIdx]; in LowerCall()1302 CCValAssign &VA = ArgLocs[ArgRegIdx]; in LowerCall()1324 if (ArgRegIdx != NumArgRegs) { in LowerCall()