Searched refs:B12 (Results 1 – 25 of 83) sorted by relevance
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510 15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4;512 B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX;526 const Instr kCmpCmnMask = 0xDD * B20 | 0xF * B12;1243 emit(instr | rd.code() * B12); in AddrMode1()1245 emit(instr | rn.code() * B16 | rd.code() * B12); in AddrMode1()1312 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12); in AddrMode2()1361 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12); in AddrMode3()1392 emit(instr | am | x.rn_.code()*B16 | crd.code()*B12 | offset_8); in AddrMode5()1454 emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BLX | target.code()); in blx()1459 emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BX | target.code()); in bx()[all …]
174 B12 = 1 << 12, enumerator
12 %B12 = and i8 %L13, %L1013 %B35 = and i8 %B12, %L1016 %B38 = urem i8 %B35, %B12
24 br label %B1226 B12:40 br label %B12
64 %B12 = lshr i32 %B7, %and1, !dbg !1465 %C1 = icmp ult i32 %and1, %B1267 %cmp2 = icmp eq i32 0, %B12
46 …"."), B10('B', 10, "/"), B11('B', 11, "(key to right of /)"), B12('B', 12, "(2 keys to right of /)… enumConstant
619 (static_cast<int32_t>(rt)*B12) | B11 | B9 |635 (static_cast<int32_t>(rt)*B12) | B11 | B9 |657 (static_cast<int32_t>(rt)*B12) | B11 | B9 | in vmovsrr()680 (static_cast<int32_t>(rt)*B12) | B11 | B9 | in vmovrrs()699 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |720 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |742 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |756 ((static_cast<int32_t>(sd) >> 1)*B12) |770 ((static_cast<int32_t>(sd) >> 1)*B12) |782 ((static_cast<int32_t>(dd) & 0xf)*B12) |[all …]
228 def B12 : AArch64Reg<12, "b12">, DwarfRegNum<[76]>;262 def H12 : AArch64Reg<12, "h12", [B12]>, DwarfRegAlias<B12>;297 def S12 : AArch64Reg<12, "s12", [H12]>, DwarfRegAlias<B12>;332 def D12 : AArch64Reg<12, "d12", [S12], ["v12", ""]>, DwarfRegAlias<B12>;367 def Q12 : AArch64Reg<12, "q12", [D12], ["v12", ""]>, DwarfRegAlias<B12>;
124 case AArch64::D12: return AArch64::B12; in getBRegFromDReg()164 case AArch64::B12: return AArch64::D12; in getDRegFromBReg()
16 // CHECK: def B12 {
15 …41*85.A;0I@2LA1^C3�B2�C8�CF�>B�?=�?-�@,�@+�>-�=+�>,�@3�D7i>394372/41-/0-3--B12�PP�t�XU�[Vg��~dd[--…
247 def B12 : AArch64Reg<12, "b12">, DwarfRegNum<[76]>;281 def H12 : AArch64Reg<12, "h12", [B12]>, DwarfRegAlias<B12>;316 def S12 : AArch64Reg<12, "s12", [H12]>, DwarfRegAlias<B12>;351 def D12 : AArch64Reg<12, "d12", [S12], ["v12", ""]>, DwarfRegAlias<B12>;386 def Q12 : AArch64Reg<12, "q12", [D12], ["v12", ""]>, DwarfRegAlias<B12>;
300 %B12 = extractelement <16 x float> %B, i32 12301 %sub12 = fsub float %A12, %B12569 %B12 = extractelement <16 x float> %B, i32 12570 %sub12 = fadd float %A12, %B12
781 1B12=1B11 1B351818 FACD>9B122412 2FA0A>9B12
104 0B11..0B12; ; UNASSIGNED
45 …C11, C12, C13, B00, B01, B02, B03, B04, B05, B06, B07, B08, B09, B10, B11, B12, B13, A00, A01, A02… enumConstant
112 0B11..0B12; ; UNASSIGNED
113 0B11..0B12; ; UNASSIGNED
48 static constexpr IValueT B12 = 1 << 12; variable1068 B25 | B24 | B20 | B15 | B14 | B13 | B12 | B4 | in emitDivOp()1521 B21 | B20 | B19 | B18 | B17 | B16 | B15 | B14 | B13 | B12 | B6 | B4 | in dmb()1848 B24 | B21 | B15 | B14 | B13 | B12; in nop()3291 B13 | B12 | B11 | B9 | B4 | in vmrsAPSR_nzcv()