| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-2013-01-23-sext-crash.ll | 7 %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
14 %FC70 = sitofp <4 x i32> %B17 to <4 x double>
21 %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
28 %FC70 = uitofp <4 x i32> %B17 to <4 x double>
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-2013-01-23-sext-crash.ll | 7 %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
14 %FC70 = sitofp <4 x i32> %B17 to <4 x double>
21 %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
28 %FC70 = uitofp <4 x i32> %B17 to <4 x double>
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/ADCE/ |
| D | 2016-09-06.ll | 34 br label %B17
36 B17:
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 233 def B17 : AArch64Reg<17, "b17">, DwarfRegNum<[81]>;
267 def H17 : AArch64Reg<17, "h17", [B17]>, DwarfRegAlias<B17>;
302 def S17 : AArch64Reg<17, "s17", [H17]>, DwarfRegAlias<B17>;
337 def D17 : AArch64Reg<17, "d17", [S17], ["v17", ""]>, DwarfRegAlias<B17>;
372 def Q17 : AArch64Reg<17, "q17", [D17], ["v17", ""]>, DwarfRegAlias<B17>;
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 129 case AArch64::D17: return AArch64::B17; in getBRegFromDReg()
169 case AArch64::B17: return AArch64::D17; in getDRegFromBReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 129 case AArch64::D17: return AArch64::B17; in getBRegFromDReg()
169 case AArch64::B17: return AArch64::D17; in getDRegFromBReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | combine-srem.ll | 421 %B17 = or i32 0, 2147483647
424 %B13 = udiv i32 %B17, %B17
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 252 def B17 : AArch64Reg<17, "b17">, DwarfRegNum<[81]>;
286 def H17 : AArch64Reg<17, "h17", [B17]>, DwarfRegAlias<B17>;
321 def S17 : AArch64Reg<17, "s17", [H17]>, DwarfRegAlias<B17>;
356 def D17 : AArch64Reg<17, "d17", [S17], ["v17", ""]>, DwarfRegAlias<B17>;
391 def Q17 : AArch64Reg<17, "q17", [D17], ["v17", ""]>, DwarfRegAlias<B17>;
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 53 static constexpr IValueT B17 = 1 << 17; variable
1258 B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B9 | Opcode; in emitSIMDCvtqq()
1521 B21 | B20 | B19 | B18 | B17 | B16 | B15 | B14 | B13 | B12 | B6 | B4 | in dmb()
2142 B17 | B16 | B11 | B10 | B9 | B8 | B5 | B4; in rbit()
2153 constexpr IValueT RevOpcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 | in rev()
2625 B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6; in vcvtsd()
2780 constexpr IValueT VcvtdsOpcode = B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6; in vcvtds()
3501 constexpr IValueT VzipOpcode = B25 | B24 | B23 | B21 | B20 | B17 | B8 | B7; in vzip()
3506 constexpr IValueT VtrnOpcode = B25 | B24 | B23 | B21 | B20 | B17 | B7; in vzip()
3922 IValueT VqmovnOpcode = B25 | B24 | B23 | B21 | B20 | B17 | B9 | in vqmovn2()
|
| /external/v8/src/arm/ |
| D | constants-arm.h | 176 B17 = 1 << 17, enumerator
|
| D | assembler-arm.cc | 3848 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | 0x3 * B17 | vd * B12 | in vrintz()
3862 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | 0x3 * B17 | vd * B12 | in vrintz()
4113 op_encoding = B17; in EncodeNeonUnaryOp()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/ |
| D | llvm-stress-s2704903805.ll | 45 %B17 = lshr <2 x i16> zeroinitializer, %B
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | llvm-stress-s2704903805.ll | 45 %B17 = lshr <2 x i16> zeroinitializer, %B
|
| /external/u-boot/arch/arm/dts/ |
| D | am335x-icev2.dts | 183 AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
|
| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.cc | 1105 EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm);
1110 EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm);
1358 EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord, in vrecpeqs()
1369 EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8 | B7, in vrsqrteqs()
1421 EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B8 | B7, kByte, qd, Q0, qm); in vzipqw()
|
| D | assembler_arm.h | 60 B17 = 1 << 17,
|
| /external/ImageMagick/PerlMagick/t/reference/write/jng/ |
| D | read_prog_jdaa.miff | 13 …;0�991�872�:65�956�734�602�61.�61+�73*�56&�6;%�7<%�><-�E<3�K;;�L7<�G3<�C/8�B17�F35�K2.�O*"�Y"�j$…
|
| D | read_jdaa.miff | 13 …;0�991�872�:65�956�734�602�61.�61+�73*�56&�6;%�7<%�><-�E<3�K;;�L7<�G3<�C/8�B17�F35�K2.�O*"�Y"�j$…
|
| D | read_idat.miff | 13 …;0�991�872�:65�956�734�602�61.�61+�73*�56&�6;%�7<%�><-�E<3�K;;�L7<�G3<�C/8�B17�F35�K2.�O*"�Y"�j$…
|
| D | read_prog_idat.miff | 13 …;0�991�872�:65�956�734�602�61.�61+�73*�56&�6;%�7<%�><-�E<3�K;;�L7<�G3<�C/8�B17�F35�K2.�O*"�Y"�j$…
|
| /external/icu/android_icu4j/src/main/tests/android/icu/dev/data/ |
| D | IDNATestInput.txt | 256 namebase: <0B15><0B16><0B17>
|
| /external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/ |
| D | IDNATestInput.txt | 256 namebase: <0B15><0B16><0B17>
|
| /external/icu/icu4c/source/test/testdata/ |
| D | idna_conf.txt | 256 namebase: <0B15><0B16><0B17>
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 351 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
|
| /external/v8/src/ppc/ |
| D | constants-ppc.h | 2585 B17 = 1 << 17, enumerator
|