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Searched refs:B22 (Results 1 – 25 of 64) sorted by relevance

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/external/v8/src/arm/
Dassembler-arm.cc516 const Instr kMovMvnFlip = B22;
616 return (instr & (B27 | B26 | B25 | B22 | B20)) == (B26 | B20); in IsLdrRegisterImmediate()
668 return (instr & (B27 | B26 | B25 | B22 | B20)) == B26; in IsStrRegisterImmediate()
685 return (instr & (B27 | B26 | B25 | B24 | B23 | B22 | B21)) == (B25 | B23); in IsAddRegisterImmediate()
1698 emit(cond | B22 | B21 | dst.code()*B16 | srcA.code()*B12 | in mls()
1732 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | in smmla()
1740 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | 0xF * B12 | in smmul()
1753 emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 | in smlal()
1766 emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 | in smull()
1800 emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 | in clz()
[all …]
Dconstants-arm.h181 B22 = 1 << 22, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
Ddag-combine-ossfuzz-crash.ll25 %B22 = udiv i66 %B9, %B1
37 %B16 = urem i66 %B22, %L6
/external/llvm/test/CodeGen/Mips/msa/
Dllvm-stress-s1935737938.ll50 %B22 = urem i32 135673, %3
61 %Cmp31 = icmp eq i32 %B22, %B22
99 %I56 = insertelement <4 x i32> %I42, i32 %B22, i32 2
Dllvm-stress-s1704963983.ll50 %B22 = urem <8 x i64> %Shuff7, %I21
112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
Dllvm-stress-s3997499501.ll60 %B22 = sdiv <4 x i64> %Shuff7, zeroinitializer
69 …%Shuff26 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %B22, <4 x i32> <i32 undef, i32 unde…
Dllvm-stress-s3926023935.ll50 %B22 = fadd double 0.000000e+00, %BC
Dllvm-stress-s997348632.ll50 %B22 = xor <8 x i32> %I14, %I14
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Dllvm-stress-s1935737938.ll50 %B22 = urem i32 135673, %3
61 %Cmp31 = icmp eq i32 %B22, %B22
99 %I56 = insertelement <4 x i32> %I42, i32 %B22, i32 2
Dllvm-stress-s1704963983.ll50 %B22 = urem <8 x i64> %Shuff7, %I21
112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
Dllvm-stress-s3997499501.ll60 %B22 = sdiv <4 x i64> %Shuff7, zeroinitializer
69 …%Shuff26 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %B22, <4 x i32> <i32 undef, i32 unde…
Dllvm-stress-s3926023935.ll50 %B22 = fadd double 0.000000e+00, %BC
Dllvm-stress-s997348632.ll50 %B22 = xor <8 x i32> %I14, %I14
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dudiv-simplify.ll80 %B22 = add i177 %B9, %B13
82 %C9 = icmp ult i177 %Y, %B22
/external/swiftshader/third_party/subzero/src/DartARM32/
Dassembler_arm.cc37 return (encoding_ & ~kOffset12Mask) | B22 |
329 B24 | B22 | B21 | (0xf << 16) |
349 B25 | B24 | B22 | ((imm16 >> 12) << 16) |
400 EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
411 EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm); in smull()
438 EmitMulOp(AL, B22, rd_lo, rd_hi, rn, rm); in umaal()
595 B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf; in clrex()
655 B27 | B26 | B22 | in vmovsrr()
678 B27 | B26 | B22 | B20 | in vmovrrs()
718 B27 | B26 | B22 |
[all …]
Dassembler_arm.h65 B22 = 1 << 22,
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td238 def B22 : AArch64Reg<22, "b22">, DwarfRegNum<[86]>;
272 def H22 : AArch64Reg<22, "h22", [B22]>, DwarfRegAlias<B22>;
307 def S22 : AArch64Reg<22, "s22", [H22]>, DwarfRegAlias<B22>;
342 def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>;
377 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h134 case AArch64::D22: return AArch64::B22; in getBRegFromDReg()
174 case AArch64::B22: return AArch64::D22; in getDRegFromBReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h134 case AArch64::D22: return AArch64::B22; in getBRegFromDReg()
174 case AArch64::B22: return AArch64::D22; in getDRegFromBReg()
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp58 static constexpr IValueT B22 = 1 << 22; variable
444 Value = Value | B22 | ((Imm8 & 0xf0) << 4) | (Imm8 & 0x0f); in encodeImmRegOffsetEnc3()
1471 B24 | B22 | B21 | (0xF << 16) | (0xf << 8) | B4; in clz()
1520 (encodeCondition(CondARM32::kNone) << kConditionShift) | B26 | B24 | B22 | in dmb()
1775 IValueT Opcode = B25 | B24 | (IsMovW ? 0 : B22); in emitMovwt()
2098 constexpr IValueT MlsOpcode = B22 | B21; in mls()
2141 constexpr IValueT RbitOpcode = B26 | B25 | B23 | B22 | B21 | B20 | B19 | B18 | in rbit()
2319 constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; in uxt()
3103 IValueT Encoding = B27 | B26 | B22 | B11 | B9 | B8 | B4 | in vmovdrr()
3155 IValueT Encoding = B27 | B26 | B22 | B20 | B11 | B9 | B8 | B4 | in vmovrrd()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td257 def B22 : AArch64Reg<22, "b22">, DwarfRegNum<[86]>;
291 def H22 : AArch64Reg<22, "h22", [B22]>, DwarfRegAlias<B22>;
326 def S22 : AArch64Reg<22, "s22", [H22]>, DwarfRegAlias<B22>;
361 def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>;
396 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp352 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
/external/icu/icu4c/source/data/unidata/norm2/
Dnfc.txt740 0B5D>0B22 0B3C
/external/v8/src/ppc/
Dconstants-ppc.h2574 B22 = 1 << 22, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp393 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,

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