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Searched refs:BATL_PP_RW (Results 1 – 25 of 25) sorted by relevance

/external/u-boot/include/configs/
DMPC8610HPCD.h294 #define CONFIG_SYS_DBAT0L (BATL_PP_RW)
295 #define CONFIG_SYS_IBAT0L (BATL_PP_RW)
304 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
307 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
315 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
318 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
326 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
329 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
334 | BATL_PP_RW | BATL_CACHEINHIBIT \
339 | BATL_PP_RW | BATL_CACHEINHIBIT)
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Dxpedite517x.h321 BATL_PP_RW |\
329 BATL_PP_RW |\
338 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
340 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
348 BATL_PP_RW |\
356 BATL_PP_RW |\
365 BATL_PP_RW |\
373 BATL_PP_RW |\
382 BATL_PP_RW |\
390 BATL_PP_RW |\
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Dsbc8641d.h343 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
345 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
354 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
357 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
364 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
367 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
374 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
377 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
382 | BATL_PP_RW | BATL_CACHEINHIBIT \
387 | BATL_PP_RW | BATL_CACHEINHIBIT)
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DMPC8641HPCN.h430 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
431 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
438 | BATL_PP_RW | BATL_CACHEINHIBIT | \
444 | BATL_PP_RW | BATL_MEMCOHERENCE)
456 | BATL_PP_RW | BATL_CACHEINHIBIT \
462 | BATL_PP_RW | BATL_CACHEINHIBIT)
467 | BATL_PP_RW | BATL_CACHEINHIBIT | \
473 | BATL_PP_RW | BATL_CACHEINHIBIT)
482 | BATL_PP_RW | BATL_CACHEINHIBIT \
488 | BATL_PP_RW | BATL_CACHEINHIBIT)
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DTQM834x.h321 | BATL_PP_RW \
328 | BATL_PP_RW \
337 | BATL_PP_RW \
348 | BATL_PP_RW \
355 | BATL_PP_RW \
363 | BATL_PP_RW \
381 | BATL_PP_RW \
391 | BATL_PP_RW \
DMPC837XEMDS.h494 | BATL_PP_RW \
504 | BATL_PP_RW \
515 | BATL_PP_RW \
527 | BATL_PP_RW \
539 | BATL_PP_RW \
546 | BATL_PP_RW \
552 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
563 | BATL_PP_RW \
573 | BATL_PP_RW \
DMPC832XEMDS.h426 | BATL_PP_RW \
437 | BATL_PP_RW \
449 | BATL_PP_RW \
461 | BATL_PP_RW \
468 | BATL_PP_RW \
479 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
490 | BATL_PP_RW \
500 | BATL_PP_RW \
DMPC837XERDB.h510 | BATL_PP_RW \
520 | BATL_PP_RW \
531 | BATL_PP_RW \
543 | BATL_PP_RW \
555 | BATL_PP_RW \
562 | BATL_PP_RW \
568 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
579 | BATL_PP_RW \
589 | BATL_PP_RW \
DMPC8323ERDB.h344 | BATL_PP_RW \
355 | BATL_PP_RW \
367 | BATL_PP_RW \
374 | BATL_PP_RW \
385 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
396 | BATL_PP_RW \
406 | BATL_PP_RW \
Dvme8349.h405 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
413 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
417 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
429 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
433 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
445 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
450 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
455 BATL_PP_RW | BATL_MEMCOHERENCE)
DMPC8315ERDB.h461 | BATL_PP_RW \
472 | BATL_PP_RW \
484 | BATL_PP_RW \
491 | BATL_PP_RW \
497 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
507 | BATL_PP_RW \
518 | BATL_PP_RW \
Dsbc8349.h490 | BATL_PP_RW \
501 | BATL_PP_RW \
508 | BATL_PP_RW \
524 | BATL_PP_RW \
531 | BATL_PP_RW \
547 | BATL_PP_RW \
557 | BATL_PP_RW \
DMPC8349ITX.h545 | BATL_PP_RW \
555 | BATL_PP_RW \
562 | BATL_PP_RW \
578 | BATL_PP_RW \
585 | BATL_PP_RW \
601 | BATL_PP_RW \
611 | BATL_PP_RW \
Dtuxx1.h158 BATL_PP_RW | \
166 BATL_PP_RW | \
178 BATL_PP_RW | \
185 BATL_PP_RW | \
Dve8313.h368 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
376 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
382 | BATL_PP_RW \
404 | BATL_PP_RW \
413 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
417 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
DMPC8349EMDS.h578 | BATL_PP_RW \
589 | BATL_PP_RW \
596 | BATL_PP_RW \
612 | BATL_PP_RW \
619 | BATL_PP_RW \
635 | BATL_PP_RW \
645 | BATL_PP_RW \
Dsuvd3.h128 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
132 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
143 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
147 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
Dmpc8308_p1m.h406 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
414 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
422 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
426 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
432 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
DMPC8308RDB.h441 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
449 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
457 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
461 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
467 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Dhrcon.h535 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
543 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
551 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
555 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
561 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Dstrider.h567 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
575 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
583 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
587 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
593 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
DMPC8313ERDB.h538 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
545 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
551 | BATL_PP_RW \
567 | BATL_PP_RW \
576 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
/external/u-boot/include/configs/km/
Dkm83xx-common.h229 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
237 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
245 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
249 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
254 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
258 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
263 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
/external/u-boot/arch/powerpc/cpu/mpc86xx/
Dmp.c111 bootpg | BATL_PP_RW | BATL_MEMCOHERENCE); in setup_mp()
/external/u-boot/arch/powerpc/include/asm/
Dmmu.h176 #define BATL_PP_RW BATL_PP_10 macro