Home
last modified time | relevance | path

Searched refs:BFE (Results 1 – 25 of 73) sorted by relevance

123

/external/llvm/test/CodeGen/AMDGPU/
Dllvm.AMDGPU.bfe.i32.ll56 ; EG-NOT: BFE
66 ; EG-NOT: BFE
186 ; EG-NOT: BFE
198 ; EG-NOT: BFE
210 ; EG-NOT: BFE
222 ; EG-NOT: BFE
234 ; EG-NOT: BFE
246 ; EG-NOT: BFE
258 ; EG-NOT: BFE
270 ; EG-NOT: BFE
[all …]
Dshift-and-i64-ubfe.ll3 ; Make sure 64-bit BFE pattern does a 32-bit BFE on the relevant half.
41 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1
43 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
57 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 20, 1
59 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
89 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1{{$}}
105 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 20, 2
107 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
121 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 30
123 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
[all …]
Dllvm.AMDGPU.bfe.u32.ll46 ; EG-NOT: BFE
56 ; EG-NOT: BFE
334 ; EG-NOT: BFE
346 ; EG-NOT: BFE
358 ; EG-NOT: BFE
370 ; EG-NOT: BFE
382 ; EG-NOT: BFE
394 ; EG-NOT: BFE
406 ; EG-NOT: BFE
418 ; EG-NOT: BFE
[all …]
Dsdiv.ll87 ; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 8
88 ; SI: buffer_store_dword [[BFE]]
101 ; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 23
102 ; SI: buffer_store_dword [[BFE]]
115 ; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 24
116 ; SI: buffer_store_dword [[BFE]]
Dsext-eliminate.ll8 ; EG-NOT: BFE
20 ; EG-NOT: BFE
Dsext-in-reg-failure-r600.ll7 ; EG-NOT: BFE
Dshift-i64-opts.ll58 ; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[HI]], 8, 23
60 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
Dsext-in-reg.ll239 ; EG-NOT: BFE
260 ; EG-NOT: BFE
485 ; Make sure there isn't a redundant BFE
582 ; Make sure we propagate the VALUness to users of a moved scalar BFE.
Dload-global-i1.ll233 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}}
234 ; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
Dload-local-i1.ll233 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}}
234 ; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
Dload-constant-i1.ll233 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}}
234 ; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dshift-and-i64-ubfe.ll4 ; Make sure 64-bit BFE pattern does a 32-bit BFE on the relevant half.
43 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1
45 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
59 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 20, 1
61 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
93 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1{{$}}
95 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO1]]{{\]}}
109 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 20, 2
111 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
125 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 30
[all …]
Dllvm.amdgcn.ubfe.ll325 ; EG-NOT: BFE
337 ; EG-NOT: BFE
349 ; EG-NOT: BFE
361 ; EG-NOT: BFE
373 ; EG-NOT: BFE
385 ; EG-NOT: BFE
397 ; EG-NOT: BFE
409 ; EG-NOT: BFE
421 ; EG-NOT: BFE
433 ; EG-NOT: BFE
[all …]
Dbfe-combine.ll6 ; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 8, 8
7 ; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], 2, v[[BFE]]
27 ; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 16, 16
28 ; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], {{[^,]+}}, v[[BFE]]
Dsdiv.ll88 ; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 8
89 ; SI: buffer_store_dword [[BFE]]
102 ; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 23
103 ; SI: buffer_store_dword [[BFE]]
116 ; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 24
117 ; SI: buffer_store_dword [[BFE]]
Dbfe-patterns.ll28 ; SI-NEXT: v_lshr_b32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
31 ; VI-NEXT: v_lshrrev_b32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
33 ; GCN: [[BFE]]
104 ; SI-NEXT: v_ashr_i32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
107 ; VI-NEXT: v_ashrrev_i32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
109 ; GCN: [[BFE]]
Dsext-eliminate.ll8 ; EG-NOT: BFE
20 ; EG-NOT: BFE
Dsext-in-reg.ll262 ; EG-NOT: BFE
283 ; EG-NOT: BFE
460 ; Make sure we propagate the VALUness to users of a moved scalar BFE.
524 ; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x10000
525 ; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
543 ; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x20000
544 ; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
561 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[VAL]], 0, 1{{$}}
563 ; GCN: ds_write_b16 v{{[0-9]+}}, [[BFE]]
583 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[REG]], 0, 1{{$}}
[all …]
Dcgp-bitfield-extract.ll124 ; VI: s_bfe_u32 [[BFE:s[0-9]+]], [[ARG]], 0xc0004
128 ; VI: s_and_b32 s{{[0-9]+}}, [[BFE]], 0xff
132 ; VI: s_and_b32 s{{[0-9]+}}, [[BFE]], 0x7f
159 ; 32-bit BFE on one half of the integer.
Dsext-in-reg-failure-r600.ll5 ; EG-NOT: BFE
Dllvm.amdgcn.sbfe.ll384 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 0, 24
385 ; GCN: buffer_store_dword [[BFE]],
397 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 1, 16
398 ; GCN: v_lshrrev_b32_e32 [[TMP0:v[0-9]+]], 31, [[BFE]]
399 ; GCN: v_add_{{[iu]}}32_e32 [[TMP1:v[0-9]+]], vcc, [[TMP0]], [[BFE]]
456 ; Make sure there isn't a redundant BFE
Dshift-i64-opts.ll58 ; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[HI]], 8, 23
60 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
Dload-constant-i1.ll233 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}}
234 ; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
/external/mesa3d/src/intel/compiler/
Dbrw_vec4.h220 EMIT3(BFE)
Dbrw_vec4_builder.h401 ALU3(BFE) in ALU2_ACC()

123