| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | negative-immediates.s | 121 BICS r0, r1, #0xFFFFFF00
124 # CHECK-DISABLED: BICS
125 BICS.W r0, r1, #0xFFFFFF00
128 # CHECK-DISABLED: BICS.W
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| D | thumb2-narrow-dp.ll | 818 BICS r3, r2, r1 // Must be wide - 3 distinct registers
819 BICS r2, r2, r1 // Should choose narrow
820 BICS r1, r2, r1 // Should choose wide - not commutative
821 BICS.W r2, r2, r1 // Explicitly wide
822 BICS.W r0, r1, r0
824 BICS r7, r7, r1 // Should use narrow
825 BICS r8, r1, r8 // high registers so must use wide encoding
826 BICS r8, r8, r1
827 BICS r7, r8, r7
828 BICS r5, r5, r8
[all …]
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| D | basic-thumb-instructions.s | 160 @ BICS
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| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_rescale_subbandsamples.s | 114 BICS R7, R3, #1
162 BICS R7, R3, #1
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 818 BICS r3, r2, r1 // Must be wide - 3 distinct registers
819 BICS r2, r2, r1 // Should choose narrow
820 BICS r1, r2, r1 // Should choose wide - not commutative
821 BICS.W r2, r2, r1 // Explicitly wide
822 BICS.W r0, r1, r0
824 BICS r7, r7, r1 // Should use narrow
825 BICS r8, r1, r8 // high registers so must use wide encoding
826 BICS r8, r8, r1
827 BICS r7, r8, r7
828 BICS r5, r5, r8
[all …]
|
| D | basic-thumb-instructions.s | 160 @ BICS
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-rm-t32.json | 72 "Bics", // BICS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
73 // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-const-a32.json | 39 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
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| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 36 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
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| D | cond-rd-rn-operand-const-t32.json | 45 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 42 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 42 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-a32.json | 47 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 310 "BICS?ri", "CLZ", "EORri", "MVNS?r", "ORRri", "RSBS?ri", "RSCri", "SBCri",
315 "ANDS?rr", "BICS?rr", "CRC", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr",
319 "ANDS?rsi", "BICS?rsi", "EORrsi", "ORRrsi", "RSBrsi", "RSCrsi", "SBCrsi",
323 (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr",
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 79 # BICS
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 83 # BICS
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 83 # BICS
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 586 BICS = ANDS | NOT enumerator
630 BICS_w = LogicalShiftedFixed | BICS,
631 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
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| D | macro-assembler-arm64-inl.h | 59 LogicalMacro(rd, rn, operand, BICS); in Bics()
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 139 @ BICS
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 551 BICS = ANDS | NOT enumerator
595 BICS_w = LogicalShiftedFixed | BICS,
596 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
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| D | macro-assembler-aarch64.cc | 764 LogicalMacro(rd, rn, operand, BICS); in Bics()
844 case BICS: in LogicalMacro()
863 case BICS: in LogicalMacro()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX2T99.td | 427 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
449 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
468 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
|