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Searched refs:BLTZ (Results 1 – 25 of 29) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrInfo.cpp230 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || in GetAnalyzableBrOpc()
246 case Mips::BGEZ : return Mips::BLTZ; in GetOppositeBranchOpc()
247 case Mips::BLTZ : return Mips::BGEZ; in GetOppositeBranchOpc()
DMipsInstrInfo.td733 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/longbranch/
Dbranch-limits-int.mir213 ; MIPS: BLTZ $at, %bb.2, implicit-def $at {
232 ; PIC: BLTZ $at, %bb.3, implicit-def $at {
559 BLTZ killed renamable $at, %bb.2, implicit-def $at
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp413 case Mips::BGEZ: return Mips::BLTZ; in getOppositeBranchOpc()
414 case Mips::BLTZ: return Mips::BGEZ; in getOppositeBranchOpc()
510 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || in getAnalyzableBrOpc()
DMipsInstrInfo.cpp337 case Mips::BLTZ: in getEquivalentCompactForm()
DMipsInstrInfo.td1878 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp297 case Mips::BLTZ: case Mips::BLTZ64: in isBranchOffsetInRange()
515 case Mips::BLTZ: in getEquivalentCompactForm()
DMipsSEInstrInfo.cpp495 case Mips::BGEZ: return Mips::BLTZ; in getOppositeBranchOpc()
496 case Mips::BLTZ: return Mips::BGEZ; in getOppositeBranchOpc()
647 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || in getAnalyzableBrOpc()
DMipsScheduleP5600.td65 BGEZALL, BGEZL, BGTZ, BGTZL, BLEZ, BLEZL, BLTZ,
DMipsInstrInfo.td2236 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
/external/v8/src/mips/
Dconstants-mips.h579 BLTZ = ((0U << 3) + 0) << 16, enumerator
1881 case BLTZ: in IsForbiddenAfterBranchInstr()
Ddisasm-mips.cc1737 case BLTZ: in DecodeTypeImmediate()
Dassembler-mips.cc534 (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ || in IsBranch()
1702 GenInstrImmediate(REGIMM, rs, BLTZ, offset); in bltz()
Dsimulator-mips.cc6458 case BLTZ: in DecodeTypeImmediate()
/external/v8/src/mips64/
Dconstants-mips64.h606 BLTZ = ((0U << 3) + 0) << 16, enumerator
1964 case BLTZ: in IsForbiddenAfterBranchInstr()
Ddisasm-mips64.cc1939 case BLTZ: in DecodeTypeImmediateREGIMM()
Dassembler-mips64.cc513 (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ || in IsBranch()
1682 GenInstrImmediate(REGIMM, rs, BLTZ, offset); in bltz()
Dsimulator-mips64.cc6697 case BLTZ: in DecodeTypeImmediate()
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_common.c123 #define BLTZ (HI(1) | (0 << 16)) macro
1774 inst = BLTZ; in sljit_emit_cmp()
1788 inst = BLTZ; in sljit_emit_cmp()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp1548 case Mips::BLTZ: in processInstruction()
2847 ZeroTrgOpcode = Mips::BLTZ; in expandCondBranches()
2879 ZeroSrcOpcode = Mips::BLTZ; in expandCondBranches()
2893 TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp1849 case Mips::BLTZ: in processInstruction()
3757 ZeroTrgOpcode = Mips::BLTZ; in expandCondBranches()
3792 ZeroSrcOpcode = Mips::BLTZ; in expandCondBranches()
3806 TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc260 25280U, // BLTZ
1974 0U, // BLTZ
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc775 UINT64_C(67108864), // BLTZ
5144 case Mips::BLTZ:
8501 Feature_HasStdEnc | Feature_NotInMicroMips | 0, // BLTZ = 762
DMipsGenAsmWriter.inc1990 26185U, // BLTZ
4621 0U, // BLTZ
DMipsGenInstrInfo.inc777 BLTZ = 762,
4822 …::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #762 = BLTZ
10044 { Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM },

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