| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | thumb-not-mclass.s | 12 @ BLX (immediate)
|
| D | basic-thumb-instructions.s | 151 @ BL/BLX
178 @ BL/BLX (immediate)
194 @ BLX (register)
|
| /external/llvm/test/MC/ARM/ |
| D | thumb-not-mclass.s | 12 @ BLX (immediate)
|
| D | basic-thumb-instructions.s | 151 @ BL/BLX
178 @ BL/BLX (immediate)
194 @ BLX (register)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/GlobalISel/ |
| D | arm-call-lowering.ll | 11 ; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 130 @ BL/BLX
157 @ BL/BLX (immediate)
169 @ BLX (register)
|
| D | basic-arm-instructions.s | 361 @ BL/BLX (immediate)
378 @ BLX (register)
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_32.c | 91 #define BLX 0xe12fff30 macro
275 return push_inst(compiler, BLX | RM(TMP_REG1)); in emit_blx()
501 inst[1] = BLX | RM(TMP_REG1); in inline_set_jump_addr()
2140 …PTR_FAIL_IF(push_inst(compiler, (((type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1)) & ~COND_MASK) | … in sljit_emit_jump()
2394 return push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(src)); in sljit_emit_ijump()
2399 return push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1)); in sljit_emit_ijump()
2416 FAIL_IF(push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1))); in sljit_emit_ijump()
|
| D | sljitNativeARM_T2_32.c | 116 #define BLX 0x4780 macro
1827 PTR_FAIL_IF(push_inst16(compiler, BLX | RN3(TMP_REG1))); in sljit_emit_jump()
2081 return push_inst16(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RN3(src)); in sljit_emit_ijump()
2086 return push_inst16(compiler, BLX | RN3(TMP_REG1)); in sljit_emit_ijump()
2097 return push_inst16(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RN3(TMP_REG1)); in sljit_emit_ijump()
|
| /external/v8/src/arm/ |
| D | constants-arm.h | 145 BLX = 3 << 4, enumerator
|
| D | disasm-arm.cc | 924 case BLX: in DecodeType01()
|
| D | assembler-arm.cc | 512 B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX;
1454 emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BLX | target.code()); in blx()
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 95 # BLX (register)
|
| D | basic-arm-instructions.txt | 321 # BLX (register)
330 # BLX (immediate)
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 108 # BLX (register)
|
| D | basic-arm-instructions.txt | 354 # BLX (register)
363 # BLX (immediate)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 108 # BLX (register)
|
| D | basic-arm-instructions.txt | 354 # BLX (register)
363 # BLX (immediate)
|
| /external/capstone/ |
| D | ChangeLog | 197 - BLX instruction modifies PC & LR registers.
279 - BL & BLX do not read SP, but PC register.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 519 ? ARM::BLX in lowerCall()
|
| D | ARMScheduleA57.td | 167 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ
173 def : InstRW<[A57Write_2cyc_1B_1I], (instregex "BLX", "tBLX(NS)?r")>;
|
| D | ARMExpandPseudoInsts.cpp | 1416 TII->get(Thumb ? ARM::tBLXr : ARM::BLX)); in ExpandMI()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 1074 828772U, // BLX
4294 0U, // BLX
7024 // AESD, AESE, AESIMC, AESMC, BKPT, BL, BLX, BLXi, BX, CPS1p, CRC32B, CRC...
7183 // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R...
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 141 // Target for BLX *from* thumb mode.
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 1872 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1924 (BLX GPR:$func)>,
1987 // BLX (immediate)
|