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Searched refs:BRW_MRF_COMPR4 (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_ir_vec4.h247 if (r.file == MRF && (r.nr & BRW_MRF_COMPR4)) { in regions_overlap()
252 t0.nr &= ~BRW_MRF_COMPR4; in regions_overlap()
258 } else if (s.file == MRF && (s.nr & BRW_MRF_COMPR4)) { in regions_overlap()
Dbrw_ir_fs.h209 if (r.file == MRF && (r.nr & BRW_MRF_COMPR4)) { in regions_overlap()
211 t.nr &= ~BRW_MRF_COMPR4; in regions_overlap()
218 } else if (s.file == MRF && (s.nr & BRW_MRF_COMPR4)) { in regions_overlap()
Dbrw_schedule_instructions.cpp1061 int reg = inst->dst.nr & ~BRW_MRF_COMPR4; in calculate_deps()
1066 if (inst->dst.nr & BRW_MRF_COMPR4) in calculate_deps()
1185 int reg = inst->dst.nr & ~BRW_MRF_COMPR4; in calculate_deps()
1190 if (inst->dst.nr & BRW_MRF_COMPR4) in calculate_deps()
Dbrw_fs_reg_allocate.cpp477 int reg = inst->dst.nr & ~BRW_MRF_COMPR4; in get_used_mrfs()
480 if (inst->dst.nr & BRW_MRF_COMPR4) { in get_used_mrfs()
Dbrw_eu_defines.h877 #define BRW_MRF_COMPR4 (1 << 7) macro
Dbrw_disasm.c649 _reg_nr &= ~BRW_MRF_COMPR4; in reg()
1848 brw_inst_dst_da_reg_nr(devinfo, inst) & BRW_MRF_COMPR4) { in brw_disassemble_inst()
Dbrw_fs.cpp2955 if (inst->dst.nr & BRW_MRF_COMPR4) { in compute_to_mrf()
2966 scan_inst->dst.nr &= ~BRW_MRF_COMPR4; in compute_to_mrf()
3457 dst.nr = dst.nr & ~BRW_MRF_COMPR4; in lower_load_payload()
3471 if (inst->dst.file == MRF && (inst->dst.nr & BRW_MRF_COMPR4) && in lower_load_payload()
3495 compr4_dst.nr |= BRW_MRF_COMPR4; in lower_load_payload()
3936 load->dst.nr |= BRW_MRF_COMPR4; in lower_fb_write_logical_send()
Dbrw_eu_emit.c93 assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen)); in brw_set_dest()
172 assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen)); in brw_set_src0()
Dbrw_fs_generator.cpp63 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen)); in brw_reg_from_fs_reg()
Dbrw_vec4.cpp2070 assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen)); in convert_to_hw_regs()