Searched refs:BSHFL (Results 1 – 8 of 8) sorted by relevance
/external/v8/src/mips/ |
D | constants-mips.h | 567 BSHFL = ((4U << 3) + 0), enumerator 1718 case BSHFL: { in InstructionType()
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D | assembler-mips.cc | 2547 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, BSHFL); in bitswap() 2564 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, BSHFL); in align() 2570 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, WSBH, BSHFL); in wsbh() 2575 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEH, BSHFL); in seh() 2580 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEB, BSHFL); in seb()
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D | disasm-mips.cc | 1514 case BSHFL: { in DecodeTypeRegisterSPECIAL3()
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D | simulator-mips.cc | 4147 case BSHFL: { in DecodeTypeRegisterSPECIAL3()
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/external/v8/src/mips64/ |
D | constants-mips64.h | 585 BSHFL = ((4U << 3) + 0), enumerator 1783 case BSHFL: { in InstructionType()
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D | assembler-mips64.cc | 2908 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, BSHFL); in bitswap() 2930 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, BSHFL); in align() 2943 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, WSBH, BSHFL); in wsbh() 2958 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEH, BSHFL); in seh() 2963 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEB, BSHFL); in seb()
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D | disasm-mips64.cc | 1770 case BSHFL: { in DecodeTypeRegisterSPECIAL3()
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D | simulator-mips64.cc | 4252 case BSHFL: { in DecodeTypeRegisterSPECIAL3()
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