/external/v8/src/mips/ |
D | constants-mips.h | 735 BZ_B = (((3U << 3) + 0) << kRsShift), enumerator 1642 case BZ_B: in IsMSABranchInstr() 1753 case BZ_B: in InstructionType() 1905 case BZ_B: in IsForbiddenAfterBranchInstr()
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D | disasm-mips.cc | 573 case BZ_B: in PrintMsaDataFormat() 1716 case BZ_B: in DecodeTypeImmediate()
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D | assembler-mips.cc | 508 case BZ_B: in IsMsaBranch() 3238 V(bz_b, BZ_B) \
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D | simulator-mips.cc | 4256 case BZ_B: in DecodeMsaDataFormat() 6408 case BZ_B: in DecodeTypeImmediate()
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/external/v8/src/mips64/ |
D | constants-mips64.h | 769 BZ_B = (((3U << 3) + 0) << kRsShift), enumerator 1699 case BZ_B: in IsMSABranchInstr() 1837 case BZ_B: in InstructionType() 1988 case BZ_B: in IsForbiddenAfterBranchInstr()
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D | disasm-mips64.cc | 614 case BZ_B: in PrintMsaDataFormat() 1918 case BZ_B: in DecodeTypeImmediateCOP1()
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D | assembler-mips64.cc | 487 case BZ_B: in IsMsaBranch() 3555 V(bz_b, BZ_B) \
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D | simulator-mips64.cc | 4467 case BZ_B: in DecodeMsaDataFormat() 6647 case BZ_B: in DecodeTypeImmediate()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MipsSEInstrInfo.cpp | 560 case Mips::BZ_B: return Mips::BNZ_B; in getOppositeBranchOpc() 565 case Mips::BNZ_B: return Mips::BZ_B; in getOppositeBranchOpc()
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D | MipsInstrInfo.cpp | 419 case Mips::BZ_B: in isBranchOffsetInRange()
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D | MipsSEISelLowering.cpp | 1076 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B); in EmitInstrWithCustomInserter()
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D | MipsMSAInstrInfo.td | 2882 def BZ_B : BZ_B_ENC, BZ_B_DESC;
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/longbranch/ |
D | branch-limits-msa.mir | 327 BZ_B killed renamable $w0, %bb.2, implicit-def dead $at 832 ; MSA: BZ_B $w0, %bb.2, implicit-def $at { 857 ; PIC: BZ_B $w0, %bb.3, implicit-def $at {
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/external/capstone/arch/Mips/ |
D | MipsGenAsmWriter.inc | 316 17567U, // BZ_B 2030 0U, // BZ_B
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D | MipsGenDisassemblerTables.inc | 1132 /* 3021 */ MCD_OPC_Decode, 171, 2, 69, // Opcode: BZ_B
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/external/llvm/lib/Target/Mips/ |
D | MipsSEISelLowering.cpp | 1132 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B); in EmitInstrWithCustomInserter()
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D | MipsMSAInstrInfo.td | 2875 def BZ_B : BZ_B_ENC, BZ_B_DESC;
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
D | MipsGenMCCodeEmitter.inc | 842 UINT64_C(1191182336), // BZ_B 4174 case Mips::BZ_B: 8568 Feature_HasStdEnc | Feature_HasMSA | 0, // BZ_B = 829
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D | MipsGenAsmWriter.inc | 2057 17937U, // BZ_B 4688 0U, // BZ_B
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D | MipsGenInstrInfo.inc | 844 BZ_B = 829, 4889 …edSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #829 = BZ_B
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D | MipsGenDisassemblerTables.inc | 3605 /* 4214 */ MCD::OPC_Decode, 189, 6, 203, 1, // Opcode: BZ_B
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D | MipsGenAsmMatcher.inc | 5478 …{ 1693 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_…
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