/external/v8/src/mips/ |
D | constants-mips.h | 736 BZ_H = (((3U << 3) + 1) << kRsShift), enumerator 1643 case BZ_H: in IsMSABranchInstr() 1754 case BZ_H: in InstructionType() 1906 case BZ_H: in IsForbiddenAfterBranchInstr()
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D | disasm-mips.cc | 577 case BZ_H: in PrintMsaDataFormat() 1717 case BZ_H: in DecodeTypeImmediate()
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D | assembler-mips.cc | 509 case BZ_H: in IsMsaBranch() 3239 V(bz_h, BZ_H) \
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D | simulator-mips.cc | 4260 case BZ_H: in DecodeMsaDataFormat() 6411 case BZ_H: in DecodeTypeImmediate()
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/external/v8/src/mips64/ |
D | constants-mips64.h | 770 BZ_H = (((3U << 3) + 1) << kRsShift), enumerator 1700 case BZ_H: in IsMSABranchInstr() 1838 case BZ_H: in InstructionType() 1989 case BZ_H: in IsForbiddenAfterBranchInstr()
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D | disasm-mips64.cc | 618 case BZ_H: in PrintMsaDataFormat() 1919 case BZ_H: in DecodeTypeImmediateCOP1()
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D | assembler-mips64.cc | 488 case BZ_H: in IsMsaBranch() 3556 V(bz_h, BZ_H) \
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D | simulator-mips64.cc | 4471 case BZ_H: in DecodeMsaDataFormat() 6650 case BZ_H: in DecodeTypeImmediate()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MipsSEInstrInfo.cpp | 561 case Mips::BZ_H: return Mips::BNZ_H; in getOppositeBranchOpc() 566 case Mips::BNZ_H: return Mips::BZ_H; in getOppositeBranchOpc()
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D | MipsInstrInfo.cpp | 420 case Mips::BZ_H: in isBranchOffsetInRange()
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D | MipsSEISelLowering.cpp | 1078 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H); in EmitInstrWithCustomInserter()
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D | MipsMSAInstrInfo.td | 2883 def BZ_H : BZ_H_ENC, BZ_H_DESC;
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/longbranch/ |
D | branch-limits-msa.mir | 441 BZ_H killed renamable $w0, %bb.2, implicit-def dead $at 948 ; MSA: BZ_H $w0, %bb.2, implicit-def $at { 972 ; PIC: BZ_H $w0, %bb.3, implicit-def $at {
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/external/capstone/arch/Mips/ |
D | MipsGenAsmWriter.inc | 318 21122U, // BZ_H 2032 0U, // BZ_H
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D | MipsGenDisassemblerTables.inc | 1135 /* 3033 */ MCD_OPC_Decode, 173, 2, 84, // Opcode: BZ_H
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/external/llvm/lib/Target/Mips/ |
D | MipsSEISelLowering.cpp | 1134 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H); in EmitInstrWithCustomInserter()
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D | MipsMSAInstrInfo.td | 2876 def BZ_H : BZ_H_ENC, BZ_H_DESC;
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
D | MipsGenMCCodeEmitter.inc | 844 UINT64_C(1193279488), // BZ_H 4176 case Mips::BZ_H: 8570 Feature_HasStdEnc | Feature_HasMSA | 0, // BZ_H = 831
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D | MipsGenAsmWriter.inc | 2059 21702U, // BZ_H 4690 0U, // BZ_H
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D | MipsGenInstrInfo.inc | 846 BZ_H = 831, 4891 …edSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #831 = BZ_H
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D | MipsGenDisassemblerTables.inc | 3608 /* 4229 */ MCD::OPC_Decode, 191, 6, 218, 1, // Opcode: BZ_H
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D | MipsGenAsmMatcher.inc | 5480 …{ 1703 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_…
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