Searched refs:BaseRegB (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 105 unsigned BaseRegA = 0, BaseRegB = 0; in areMemAccessesTriviallyDisjoint() local
109 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
110 if (BaseRegA == BaseRegB) { in areMemAccessesTriviallyDisjoint()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 104 unsigned BaseRegA = 0, BaseRegB = 0; in areMemAccessesTriviallyDisjoint() local
108 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
109 if (BaseRegA == BaseRegB) { in areMemAccessesTriviallyDisjoint()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 660 unsigned BaseRegA = 0, BaseRegB = 0; in areMemAccessesTriviallyDisjoint() local
677 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
678 if (BaseRegA == BaseRegB) { in areMemAccessesTriviallyDisjoint()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1646 unsigned BaseRegB = getBaseAndOffset(&MIb, OffsetB, SizeB); in areMemAccessesTriviallyDisjoint() local
1647 if (!BaseRegB || !SizeB) in areMemAccessesTriviallyDisjoint()
1650 if (BaseRegA != BaseRegB) in areMemAccessesTriviallyDisjoint()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 1081 unsigned BaseRegA = 0, BaseRegB = 0; in areMemAccessesTriviallyDisjoint() local
1098 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
1099 if (BaseRegA == BaseRegB) { in areMemAccessesTriviallyDisjoint()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1839 unsigned BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1842 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
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