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Searched refs:BeginGroup (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp52 if (SC->BeginGroup) { in getNumDecoderSlots()
100 if (SC->BeginGroup) in fitsIntoCurrentGroup()
192 if (SC->BeginGroup && SC->EndGroup) in dumpSU()
194 else if (SC->BeginGroup) in dumpSU()
343 if (SC->BeginGroup) { in groupingCost()
DSystemZSchedule.td18 def BeginGroup : SchedWrite;
DSystemZMachineScheduler.cpp255 bool AffectsGrouping = (SC->isValid() && (SC->BeginGroup || SC->EndGroup)); in releaseTopNode()
DSystemZScheduleZ196.td39 def : WriteRes<BeginGroup, []> { let BeginGroup = 1; }
44 let BeginGroup = 1;
48 let BeginGroup = 1;
89 let BeginGroup = 1;
DSystemZScheduleZEC12.td39 def : WriteRes<BeginGroup, []> { let BeginGroup = 1; }
44 let BeginGroup = 1;
48 let BeginGroup = 1;
92 let BeginGroup = 1;
DSystemZScheduleZ13.td39 def : WriteRes<BeginGroup, []> { let BeginGroup = 1; }
44 let BeginGroup = 1;
48 let BeginGroup = 1;
104 let BeginGroup = 1;
DSystemZScheduleZ14.td39 def : WriteRes<BeginGroup, []> { let BeginGroup = 1; }
44 let BeginGroup = 1;
48 let BeginGroup = 1;
104 let BeginGroup = 1;
/external/llvm/include/llvm/MC/
DMCSchedule.h109 bool BeginGroup; member
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCSchedule.h118 bool BeginGroup : 1; member
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DSubtargetEmitter.cpp1003 SCDesc.BeginGroup = false; in GenSchedClassTables()
1103 SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup"); in GenSchedClassTables()
1105 SCDesc.BeginGroup |= WriteRes->getValueAsBit("SingleIssue"); in GenSchedClassTables()
1330 << ", " << ( MCDesc.BeginGroup ? "true" : "false" ) in EmitSchedClassTables()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetSchedule.cpp92 return SC->BeginGroup; in mustBeginGroup()
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp815 SCDesc.BeginGroup = false; in GenSchedClassTables()
923 SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup"); in GenSchedClassTables()
1133 << ", " << ( MCDesc.BeginGroup ? "true" : "false" ) in EmitSchedClassTables()
/external/llvm/include/llvm/Target/
DTargetSchedule.td253 bit BeginGroup = 0;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSchedule.td259 bit BeginGroup = 0;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc273 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
1293 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenSubtargetInfo.inc1514 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
2500 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
3486 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
4472 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
5458 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
6444 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
7430 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
8416 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
9402 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenSubtargetInfo.inc4710 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
5926 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
7142 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
8358 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
9574 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
10790 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
12006 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
13222 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
14438 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc10539 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
11946 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
13353 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
14760 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}