1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * 5 * Author: 6 * Peng Fan <Peng.Fan@freescale.com> 7 */ 8 9 #ifndef _ASM_ARCH_CLOCK_H 10 #define _ASM_ARCH_CLOCK_H 11 12 #include <common.h> 13 #include <asm/arch/crm_regs.h> 14 15 #ifdef CONFIG_SYS_MX7_HCLK 16 #define MXC_HCLK CONFIG_SYS_MX7_HCLK 17 #else 18 #define MXC_HCLK 24000000 19 #endif 20 21 #ifdef CONFIG_SYS_MX7_CLK32 22 #define MXC_CLK32 CONFIG_SYS_MX7_CLK32 23 #else 24 #define MXC_CLK32 32768 25 #endif 26 27 /* Mainly for compatible to imx common code. */ 28 enum mxc_clock { 29 MXC_ARM_CLK = 0, 30 MXC_AHB_CLK, 31 MXC_IPG_CLK, 32 MXC_UART_CLK, 33 MXC_CSPI_CLK, 34 MXC_AXI_CLK, 35 MXC_DDR_CLK, 36 MXC_ESDHC_CLK, 37 MXC_ESDHC2_CLK, 38 MXC_ESDHC3_CLK, 39 MXC_I2C_CLK, 40 }; 41 42 /* PLL supported by i.mx7d */ 43 enum pll_clocks { 44 PLL_CORE, /* Core PLL */ 45 PLL_SYS, /* System PLL*/ 46 PLL_ENET, /* Enet PLL */ 47 PLL_AUDIO, /* Audio PLL */ 48 PLL_VIDEO, /* Video PLL*/ 49 PLL_DDR, /* Dram PLL */ 50 PLL_USB, /* USB PLL, fixed at 480MHZ */ 51 }; 52 53 /* clk src for clock root gen */ 54 enum clk_root_src { 55 OSC_24M_CLK, 56 57 PLL_ARM_MAIN_800M_CLK, 58 59 PLL_SYS_MAIN_480M_CLK, 60 PLL_SYS_MAIN_240M_CLK, 61 PLL_SYS_MAIN_120M_CLK, 62 PLL_SYS_PFD0_392M_CLK, 63 PLL_SYS_PFD0_196M_CLK, 64 PLL_SYS_PFD1_332M_CLK, 65 PLL_SYS_PFD1_166M_CLK, 66 PLL_SYS_PFD2_270M_CLK, 67 PLL_SYS_PFD2_135M_CLK, 68 PLL_SYS_PFD3_CLK, 69 PLL_SYS_PFD4_CLK, 70 PLL_SYS_PFD5_CLK, 71 PLL_SYS_PFD6_CLK, 72 PLL_SYS_PFD7_CLK, 73 74 PLL_ENET_MAIN_500M_CLK, 75 PLL_ENET_MAIN_250M_CLK, 76 PLL_ENET_MAIN_125M_CLK, 77 PLL_ENET_MAIN_100M_CLK, 78 PLL_ENET_MAIN_50M_CLK, 79 PLL_ENET_MAIN_40M_CLK, 80 PLL_ENET_MAIN_25M_CLK, 81 82 PLL_DRAM_MAIN_1066M_CLK, 83 PLL_DRAM_MAIN_533M_CLK, 84 85 PLL_AUDIO_MAIN_CLK, 86 PLL_VIDEO_MAIN_CLK, 87 88 PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */ 89 90 EXT_CLK_1, 91 EXT_CLK_2, 92 EXT_CLK_3, 93 EXT_CLK_4, 94 95 REF_1M_CLK, 96 OSC_32K_CLK, 97 }; 98 99 /* 100 * Clock root index 101 */ 102 enum clk_root_index { 103 ARM_A7_CLK_ROOT = 0, 104 ARM_M4_CLK_ROOT = 1, 105 ARM_M0_CLK_ROOT = 2, 106 MAIN_AXI_CLK_ROOT = 16, 107 DISP_AXI_CLK_ROOT = 17, 108 ENET_AXI_CLK_ROOT = 18, 109 NAND_USDHC_BUS_CLK_ROOT = 19, 110 AHB_CLK_ROOT = 32, 111 DRAM_PHYM_CLK_ROOT = 48, 112 DRAM_CLK_ROOT = 49, 113 DRAM_PHYM_ALT_CLK_ROOT = 64, 114 DRAM_ALT_CLK_ROOT = 65, 115 USB_HSIC_CLK_ROOT = 66, 116 PCIE_CTRL_CLK_ROOT = 67, 117 PCIE_PHY_CLK_ROOT = 68, 118 EPDC_PIXEL_CLK_ROOT = 69, 119 LCDIF_PIXEL_CLK_ROOT = 70, 120 MIPI_DSI_EXTSER_CLK_ROOT = 71, 121 MIPI_CSI_WARP_CLK_ROOT = 72, 122 MIPI_DPHY_REF_CLK_ROOT = 73, 123 SAI1_CLK_ROOT = 74, 124 SAI2_CLK_ROOT = 75, 125 SAI3_CLK_ROOT = 76, 126 SPDIF_CLK_ROOT = 77, 127 ENET1_REF_CLK_ROOT = 78, 128 ENET1_TIME_CLK_ROOT = 79, 129 ENET2_REF_CLK_ROOT = 80, 130 ENET2_TIME_CLK_ROOT = 81, 131 ENET_PHY_REF_CLK_ROOT = 82, 132 EIM_CLK_ROOT = 83, 133 NAND_CLK_ROOT = 84, 134 QSPI_CLK_ROOT = 85, 135 USDHC1_CLK_ROOT = 86, 136 USDHC2_CLK_ROOT = 87, 137 USDHC3_CLK_ROOT = 88, 138 CAN1_CLK_ROOT = 89, 139 CAN2_CLK_ROOT = 90, 140 I2C1_CLK_ROOT = 91, 141 I2C2_CLK_ROOT = 92, 142 I2C3_CLK_ROOT = 93, 143 I2C4_CLK_ROOT = 94, 144 UART1_CLK_ROOT = 95, 145 UART2_CLK_ROOT = 96, 146 UART3_CLK_ROOT = 97, 147 UART4_CLK_ROOT = 98, 148 UART5_CLK_ROOT = 99, 149 UART6_CLK_ROOT = 100, 150 UART7_CLK_ROOT = 101, 151 ECSPI1_CLK_ROOT = 102, 152 ECSPI2_CLK_ROOT = 103, 153 ECSPI3_CLK_ROOT = 104, 154 ECSPI4_CLK_ROOT = 105, 155 PWM1_CLK_ROOT = 106, 156 PWM2_CLK_ROOT = 107, 157 PWM3_CLK_ROOT = 108, 158 PWM4_CLK_ROOT = 109, 159 FLEXTIMER1_CLK_ROOT = 110, 160 FLEXTIMER2_CLK_ROOT = 111, 161 SIM1_CLK_ROOT = 112, 162 SIM2_CLK_ROOT = 113, 163 GPT1_CLK_ROOT = 114, 164 GPT2_CLK_ROOT = 115, 165 GPT3_CLK_ROOT = 116, 166 GPT4_CLK_ROOT = 117, 167 TRACE_CLK_ROOT = 118, 168 WDOG_CLK_ROOT = 119, 169 CSI_MCLK_CLK_ROOT = 120, 170 AUDIO_MCLK_CLK_ROOT = 121, 171 WRCLK_CLK_ROOT = 122, 172 IPP_DO_CLKO1 = 123, 173 IPP_DO_CLKO2 = 124, 174 175 CLK_ROOT_MAX, 176 }; 177 178 struct clk_root_setting { 179 enum clk_root_index root; 180 u32 setting; 181 }; 182 183 /* 184 * CCGR mapping 185 */ 186 enum clk_ccgr_index { 187 CCGR_CPU = 0, 188 CCGR_M4 = 1, 189 CCGR_SIM_MAIN = 4, 190 CCGR_SIM_DISPLAY = 5, 191 CCGR_SIM_ENET = 6, 192 CCGR_SIM_M = 7, 193 CCGR_SIM_S = 8, 194 CCGR_SIM_WAKEUP = 9, 195 CCGR_IPMUX1 = 10, 196 CCGR_IPMUX2 = 11, 197 CCGR_IPMUX3 = 12, 198 CCGR_ROM = 16, 199 CCGR_OCRAM = 17, 200 CCGR_OCRAM_S = 18, 201 CCGR_DRAM = 19, 202 CCGR_RAWNAND = 20, 203 CCGR_QSPI = 21, 204 CCGR_WEIM = 22, 205 CCGR_ADC = 32, 206 CCGR_ANATOP = 33, 207 CCGR_SCTR = 34, 208 CCGR_OCOTP = 35, 209 CCGR_CAAM = 36, 210 CCGR_SNVS = 37, 211 CCGR_RDC = 38, 212 CCGR_MU = 39, 213 CCGR_HS = 40, 214 CCGR_DVFS = 41, 215 CCGR_QOS = 42, 216 CCGR_QOS_DISPMIX = 43, 217 CCGR_QOS_MEGAMIX = 44, 218 CCGR_CSU = 45, 219 CCGR_DBGMON = 46, 220 CCGR_DEBUG = 47, 221 CCGR_TRACE = 48, 222 CCGR_SEC_DEBUG = 49, 223 CCGR_SEMA1 = 64, 224 CCGR_SEMA2 = 65, 225 CCGR_PERFMON1 = 68, 226 CCGR_PERFMON2 = 69, 227 CCGR_SDMA = 72, 228 CCGR_CSI = 73, 229 CCGR_EPDC = 74, 230 CCGR_LCDIF = 75, 231 CCGR_PXP = 76, 232 CCGR_PCIE = 96, 233 CCGR_MIPI_CSI = 100, 234 CCGR_MIPI_DSI = 101, 235 CCGR_MIPI_MEM_PHY = 102, 236 CCGR_USB_CTRL = 104, 237 CCGR_USB_HSIC = 105, 238 CCGR_USB_PHY1 = 106, 239 CCGR_USB_PHY2 = 107, 240 CCGR_USDHC1 = 108, 241 CCGR_USDHC2 = 109, 242 CCGR_USDHC3 = 110, 243 CCGR_ENET1 = 112, 244 CCGR_ENET2 = 113, 245 CCGR_CAN1 = 116, 246 CCGR_CAN2 = 117, 247 CCGR_ECSPI1 = 120, 248 CCGR_ECSPI2 = 121, 249 CCGR_ECSPI3 = 122, 250 CCGR_ECSPI4 = 123, 251 CCGR_GPT1 = 124, 252 CCGR_GPT2 = 125, 253 CCGR_GPT3 = 126, 254 CCGR_GPT4 = 127, 255 CCGR_FTM1 = 128, 256 CCGR_FTM2 = 129, 257 CCGR_PWM1 = 132, 258 CCGR_PWM2 = 133, 259 CCGR_PWM3 = 134, 260 CCGR_PWM4 = 135, 261 CCGR_I2C1 = 136, 262 CCGR_I2C2 = 137, 263 CCGR_I2C3 = 138, 264 CCGR_I2C4 = 139, 265 CCGR_SAI1 = 140, 266 CCGR_SAI2 = 141, 267 CCGR_SAI3 = 142, 268 CCGR_SIM1 = 144, 269 CCGR_SIM2 = 145, 270 CCGR_UART1 = 148, 271 CCGR_UART2 = 149, 272 CCGR_UART3 = 150, 273 CCGR_UART4 = 151, 274 CCGR_UART5 = 152, 275 CCGR_UART6 = 153, 276 CCGR_UART7 = 154, 277 CCGR_WDOG1 = 156, 278 CCGR_WDOG2 = 157, 279 CCGR_WDOG3 = 158, 280 CCGR_WDOG4 = 159, 281 CCGR_GPIO1 = 160, 282 CCGR_GPIO2 = 161, 283 CCGR_GPIO3 = 162, 284 CCGR_GPIO4 = 163, 285 CCGR_GPIO5 = 164, 286 CCGR_GPIO6 = 165, 287 CCGR_GPIO7 = 166, 288 CCGR_IOMUX = 168, 289 CCGR_IOMUX_LPSR = 169, 290 CCGR_KPP = 170, 291 292 CCGR_SKIP, 293 CCGR_MAX, 294 }; 295 296 /* Clock root channel */ 297 enum clk_root_type { 298 CCM_CORE_CHANNEL, 299 CCM_BUS_CHANNEL, 300 CCM_AHB_CHANNEL, 301 CCM_DRAM_PHYM_CHANNEL, 302 CCM_DRAM_CHANNEL, 303 CCM_IP_CHANNEL, 304 }; 305 306 #include <asm/arch/clock_slice.h> 307 308 /* 309 * entry: the clock root index 310 * type: ccm channel 311 * src_mux: each entry corresponding to the clock src, detailed info in CCM RM 312 */ 313 struct clk_root_map { 314 enum clk_root_index entry; 315 enum clk_root_type type; 316 uint8_t src_mux[8]; 317 }; 318 319 enum enet_freq { 320 ENET_25MHZ, 321 ENET_50MHZ, 322 ENET_125MHZ, 323 }; 324 325 u32 get_root_clk(enum clk_root_index clock_id); 326 u32 mxc_get_clock(enum mxc_clock clk); 327 u32 imx_get_uartclk(void); 328 u32 imx_get_fecclk(void); 329 void clock_init(void); 330 #ifdef CONFIG_SYS_I2C_MXC 331 int enable_i2c_clk(unsigned char enable, unsigned i2c_num); 332 #endif 333 #ifdef CONFIG_FEC_MXC 334 int set_clk_enet(enum enet_freq type); 335 #endif 336 int set_clk_qspi(void); 337 int set_clk_nand(void); 338 #ifdef CONFIG_MXC_OCOTP 339 void enable_ocotp_clk(unsigned char enable); 340 #endif 341 void enable_usboh3_clk(unsigned char enable); 342 #ifdef CONFIG_SECURE_BOOT 343 void hab_caam_clock_enable(unsigned char enable); 344 #endif 345 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq); 346 void enable_thermal_clk(void); 347 #endif 348