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Searched refs:CCI_S1_QOS_CONTROL_BASE (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
Dlowlevel.S116 ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
126 ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
136 ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
146 ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
156 ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
166 ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
/external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
Dconfig.h89 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) macro