| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 112 Opc = Mips::CFC1; in copyPhysReg()
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| D | MipsInstrFPU.td | 172 def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs),
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| /external/v8/src/mips/ |
| D | disasm-mips.cc | 673 if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) { in FormatFPURegister()
1594 case CFC1: in DecodeTypeRegister()
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| D | constants-mips.h | 587 CFC1 = ((0U << 3) + 2) << 21, enumerator
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| D | assembler-mips.cc | 2626 GenInstrRegister(COP1, CFC1, rt, fs); in cfc1()
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| D | simulator-mips.cc | 3665 case CFC1: in DecodeTypeRegisterCOP1()
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| /external/v8/src/mips64/ |
| D | disasm-mips64.cc | 714 if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) { in FormatFPURegister()
1382 case CFC1: in DecodeTypeRegisterCOP1()
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| D | constants-mips64.h | 617 CFC1 = ((0U << 3) + 2) << 21, enumerator
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| D | assembler-mips64.cc | 3023 GenInstrRegister(COP1, CFC1, rt, fs); in cfc1()
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| D | simulator-mips64.cc | 3549 case CFC1: in DecodeTypeRegisterCOP1()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 93 Opc = Mips::CFC1; in copyPhysReg()
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| D | MipsInstrFPU.td | 364 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_common.c | 126 #define CFC1 (HI(17) | (2 << 21)) macro
1930 FAIL_IF(push_inst(compiler, CFC1 | TA(dst_ar) | DA(FCSR_REG), dst_ar)); in sljit_emit_op_flags()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 98 Opc = Mips::CFC1; in copyPhysReg()
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| D | MipsScheduleP5600.td | 552 def : InstRW<[P5600WriteMoveFPUToGPR], (instrs BC1F, BC1FL, BC1T, BC1TL, CFC1,
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| D | MipsInstrFPU.td | 483 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 941 {DBGFIELD("CFC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #666
1961 {DBGFIELD("CFC1") 2, false, false, 69, 4, 2, 1, 0, 0}, // #666
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| D | MipsGenMCCodeEmitter.inc | 883 UINT64_C(1145044992), // CFC1
5687 case Mips::CFC1:
8609 Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CFC1 = 870
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| D | MipsGenInstrInfo.inc | 885 CFC1 = 870,
3323 CFC1 = 666,
4930 …nmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #870 = CFC1
10055 { Mips::CFC1, Mips::CFC1, Mips::CFC1_MM },
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| D | MipsGenAsmWriter.inc | 2098 16482U, // CFC1
4729 0U, // CFC1
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3147 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
3148 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 363 16437U, // CFC1
2077 0U, // CFC1
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| D | MipsGenDisassemblerTables.inc | 807 /* 1605 */ MCD_OPC_Decode, 218, 2, 62, // Opcode: CFC1
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4123 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4124 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
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| /external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/ |
| D | NormalizationTest-3.2.0.txt | 11406 CFC1;CFC1;110F 116C 11C0;CFC1;110F 116C 11C0;
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