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Searched refs:CLASS_D (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/MergeICmps/X86/
Dpr36557.ll37 ; X86-NEXT: [[FAILUREREPORTINGMODE:%.*]] = getelementptr inbounds [[CLASS_D:%.*]], %class.D* [[T…
/external/v8/src/mips/
Dconstants-mips.h647 CLASS_D = ((3U << 3) + 3), enumerator
Ddisasm-mips.cc1117 case CLASS_D: in DecodeTypeRegisterRsType()
Dassembler-mips.cc3035 GenInstrRegister(COP1, D, f0, fs, fd, CLASS_D); in class_d()
Dsimulator-mips.cc2989 case CLASS_D: { // Mips32r6 instruction in DecodeTypeRegisterDRsType()
/external/v8/src/mips64/
Dconstants-mips64.h677 CLASS_D = ((3U << 3) + 3), enumerator
Ddisasm-mips64.cc1193 case CLASS_D: in DecodeTypeRegisterRsType()
Dassembler-mips64.cc3409 GenInstrRegister(COP1, D, f0, fs, fd, CLASS_D); in class_d()
Dsimulator-mips64.cc3283 case CLASS_D: { // Mips64r6 instruction in DecodeTypeRegisterDRsType()
/external/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td782 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td892 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc368 19404U, // CLASS_D
2082 0U, // CLASS_D
DMipsGenDisassemblerTables.inc3842 /* 860 */ MCD_OPC_Decode, 223, 2, 82, // Opcode: CLASS_D
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc891 UINT64_C(1176502299), // CLASS_D
3352 case Mips::CLASS_D:
8617 …tdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CLASS_D = 878
DMipsGenAsmWriter.inc2106 19875U, // CLASS_D
4737 0U, // CLASS_D
DMipsGenInstrInfo.inc893 CLASS_D = 878,
4938 …deledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #878 = CLASS_D
DMipsGenDisassemblerTables.inc6400 /* 1051 */ MCD::OPC_Decode, 238, 6, 216, 1, // Opcode: CLASS_D
DMipsGenAsmMatcher.inc5711 …{ 2098 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Fe…