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Searched refs:CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
Dwrap_pll_config.c67 CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
Dclock_manager_gen5.c410 CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET; in cm_get_l4_sp_clk_hz()
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dclock_manager_gen5.h218 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 macro