Searched refs:CLK_DDR (Results 1 – 15 of 15) sorted by relevance
| /external/u-boot/drivers/ddr/marvell/axp/ |
| D | ddr3_axp_vars.h | 167 u8 div_ratio1to1[CLK_VCO][CLK_DDR] =
196 u8 div_ratio2to1[CLK_VCO][CLK_DDR] =
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| D | ddr3_dfs.c | 40 extern u8 div_ratio[CLK_VCO][CLK_DDR];
44 extern u8 div_ratio1to1[CLK_CPU][CLK_DDR];
45 extern u8 div_ratio2to1[CLK_CPU][CLK_DDR];
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| D | ddr3_axp.h | 444 #define CLK_DDR 12 macro
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| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_rv1108.c | 45 case CLK_DDR: in rv1108_pll_id()
120 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); in rv1108_sfc_set_clk()
201 unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR); in rkclk_init()
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| D | clk_rk322x.c | 340 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg); in rk322x_ddr_set_clk()
384 case CLK_DDR: in rk322x_clk_set_rate()
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| D | clk_rk3188.c | 152 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); in rkclk_configure_ddr()
506 case CLK_DDR: in rk3188_clk_set_rate()
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| D | clk_rk3288.c | 207 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); in rkclk_configure_ddr()
755 case CLK_DDR: in rk3288_clk_set_rate()
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| D | clk_rk3368.c | 495 case CLK_DDR: in rk3368_clk_set_rate()
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| D | clk_rk3328.c | 219 case CLK_DDR: in rkclk_set_pll()
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | clock.h | 28 CLK_DDR, enumerator
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| /external/u-boot/arch/arm/mach-rockchip/ |
| D | rk3288-board.c | 262 { "dpll", CLK_DDR }, in do_clock()
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| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_rk322x.c | 802 priv->ddr_clk.id = CLK_DDR; in rk322x_dmc_probe()
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| D | dmc-rk3368.c | 939 priv->ddr_clk.id = CLK_DDR; in rk3368_dmc_probe()
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| D | sdram_rk3188.c | 906 priv->ddr_clk.id = CLK_DDR; in rk3188_dmc_probe()
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| D | sdram_rk3288.c | 1071 priv->ddr_clk.id = CLK_DDR; in rk3288_dmc_probe()
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