Searched refs:CLK_DIVIDER (Results 1 – 6 of 6) sorted by relevance
17 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) macro
28 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) macro
392 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); in clock_enable_coresight()
89 CLK_DIVIDER, /* Rx = DPLL, Tx = divider (fullduplex with */ enumerator
166 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); in tegra124_init_clocks()
158 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); in t114_init_clocks()