Searched refs:CLK_DIV_CDREX1_VAL (Results 1 – 2 of 2) sorted by relevance
507 #define CLK_DIV_CDREX1_VAL NOT_AVAILABLE macro775 #define CLK_DIV_CDREX1_VAL 0x300 macro
912 writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1); in exynos5420_system_clock_init()