Searched refs:CLK_DIV_CORE0_VAL (Results 1 – 2 of 2) sorted by relevance
133 #define CLK_DIV_CORE0_VAL 0x00120000 macro
670 writel(CLK_DIV_CORE0_VAL, &clk->div_core0); in exynos5250_system_clock_init()