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Searched refs:CLK_DIV_DISP1_0_FIMD1 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dexynos5_setup.h234 #define CLK_DIV_DISP1_0_FIMD1 (2 << 0) macro
Dclock_init_exynos5.c986 setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); in clock_init_dp_clock()