Searched refs:CLK_DIV_DMC0_VAL (Results 1 – 4 of 4) sorted by relevance
64 writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0); in system_clock_init()
92 #define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ macro
324 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); in board_clock_init()
59 #define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ macro