Searched refs:CLK_DIV_FSYS1_VAL (Results 1 – 6 of 6) sorted by relevance
69 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in system_clock_init()
489 #define CLK_DIV_FSYS1_VAL NOT_AVAILABLE macro757 #define CLK_DIV_FSYS1_VAL 0x04f13c4f macro
204 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ macro
942 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in exynos5420_system_clock_init()
329 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); in board_clock_init()
156 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ macro