Searched refs:CLK_DIV_ISP0_VAL (Results 1 – 2 of 2) sorted by relevance
483 #define CLK_DIV_ISP0_VAL 0x31 macro750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()