Searched refs:CLK_DIV_PERIC0_VAL (Results 1 – 2 of 2) sorted by relevance
664 #define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ macro841 #define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \ macro
759 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); in exynos5250_system_clock_init()952 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); in exynos5420_system_clock_init()