Home
last modified time | relevance | path

Searched refs:CLK_DIV_TOP2_VAL (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dexynos5_setup.h628 #define CLK_DIV_TOP2_VAL NOT_AVAILABLE macro
795 #define CLK_DIV_TOP2_VAL 0x11101100 macro
Dclock_init_exynos5.c921 writel(CLK_DIV_TOP2_VAL, &clk->div_top2); in exynos5420_system_clock_init()