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Searched refs:CLK_HCLK_ARM_PLL_DIV_4 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
Dclk.c122 case CLK_HCLK_ARM_PLL_DIV_4: in get_sdram_clk_rate()
/external/u-boot/arch/arm/include/asm/arch-lpc32xx/
Dclk.h80 #define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0) macro