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Searched refs:CLK_MHZ (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/board/synopsys/hsdk/
Dhsdk.c566 soc_clk_ctl("cpu-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ); in setup_clocks()
573 soc_clk_ctl("tun-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ); in setup_clocks()
580 soc_clk_ctl("axi-clk", &rate, CLK_SET | CLK_ON | CLK_MHZ); in setup_clocks()
853 if (soc_clk_ctl("cpu-clk", &rate, CLK_GET | CLK_MHZ)) in do_hsdk_clock_get()
859 if (soc_clk_ctl("tun-clk", &rate, CLK_GET | CLK_MHZ)) in do_hsdk_clock_get()
865 if (soc_clk_ctl("axi-clk", &rate, CLK_GET | CLK_MHZ)) in do_hsdk_clock_get()
880 soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ); in do_hsdk_clock_print()
881 soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ); in do_hsdk_clock_print()
882 soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ); in do_hsdk_clock_print()
883 soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ); in do_hsdk_clock_print()
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Dclk-lib.c40 priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate; in soc_clk_ctl()
60 if (ctl & CLK_MHZ) in soc_clk_ctl()
66 if ((ctl & CLK_PRINT) && (ctl & CLK_MHZ)) in soc_clk_ctl()
Dclk-lib.h18 CLK_MHZ = BIT(5) /* all values in MHZ instead of HZ */ enumerator
/external/u-boot/arch/mips/mach-pic32/
Dcpu.c21 #define CLK_MHZ(x) ((x) / 1000000) macro
153 CLK_MHZ(rate(PLLCLK))); in soc_clk_dump()
155 printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK))); in soc_clk_dump()
157 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL))); in soc_clk_dump()
161 CLK_MHZ(rate(i))); in soc_clk_dump()
165 CLK_MHZ(rate(i))); in soc_clk_dump()