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Searched refs:CLK_SRC_PERIC0_VAL (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dexynos5_setup.h641 #define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ macro
810 #define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \ macro
Dclock_init_exynos5.c758 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); in exynos5250_system_clock_init()
949 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); in exynos5420_system_clock_init()