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Searched refs:CLK_SRC_RIGHTBUS_VAL (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dclock_init_exynos4.c52 writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); in system_clock_init()
Dexynos4_setup.h165 #define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL) macro